Samsung M378B5673EH1-CF8 Datasheet

1 of 39DDR3 SDRAMRev. 1.03 July 2009Unbuffered DIMMDDR3 SDRAM Specification240pin Unbuffered DIMM based on 1Gb E-die64/72-bit Non-ECC/ECC78FBGA with

10 of 39DDR3 SDRAMRev. 1.03 July 2009Unbuffered DIMM8.1 Address Mirroring FeatureThere is a via grid located under the DRAMs for wiring the CA signal

11 of 39DDR3 SDRAMRev. 1.03 July 2009Unbuffered DIMM9.0 Function Block Diagram:9.1 1GB, 128Mx64 Module (Populated as 1 rank of x8 DDR3 SDRAMs)S0DQS0D

12 of 39DDR3 SDRAMRev. 1.03 July 2009Unbuffered DIMM9.2 1GB, 128Mx72 Module (Populated as 1 rank of x8 DDR3 SDRAMs)S0DQS0DQS0DM0DM CS DQS DQSDQ0DQ1DQ

13 of 39DDR3 SDRAMRev. 1.03 July 2009Unbuffered DIMM9.3 2GB, 256Mx64 Module (Populated as 2 ranks of x8 DDR3 SDRAMs)S0DQS0DQS0DM0DM CS DQS DQSDQ0DQ1D

14 of 39DDR3 SDRAMRev. 1.03 July 2009Unbuffered DIMM9.4 2GB, 256Mx72 ECC Module (Populated as 2 ranks of x8 DDR3 SDRAMs)S0DQS0DQS0DM0DM CS DQS DQSDQ0

15 of 39DDR3 SDRAMRev. 1.03 July 2009Unbuffered DIMM10.0 Absolute Maximum Ratings10.1 Absolute Maximum DC RatingsNote :1. Stresses greater than those

16 of 39DDR3 SDRAMRev. 1.03 July 2009Unbuffered DIMM12.0 AC & DC Input Measurement Levels 12.1 AC & DC Logic Input Levels for Single-ended Si

17 of 39DDR3 SDRAMRev. 1.03 July 2009Unbuffered DIMM12.2 VREF Tolerances The dc-tolerance limits and ac-noise limits for the reference voltages VREFC

18 of 39DDR3 SDRAMRev. 1.03 July 2009Unbuffered DIMM12.3 AC & DC Logic Input Levels for Differential Signals12.3.1 Differential Signals Definitio

19 of 39DDR3 SDRAMRev. 1.03 July 2009Unbuffered DIMM12.3.3 Single-ended Requirements for Differential SignalsEach individual component of a different

2 of 39DDR3 SDRAMRev. 1.03 July 2009Unbuffered DIMM1.0 DDR3 Registered DIMM Ordering Information ...

20 of 39DDR3 SDRAMRev. 1.03 July 2009Unbuffered DIMM12.3.4 Differential Input Cross Point VoltageTo guarantee tight setup and hold times as well as o

21 of 39DDR3 SDRAMRev. 1.03 July 2009Unbuffered DIMM13.0 AC & DC Output Measurement Levels 13.1 Single-ended AC & DC Output LevelsSingle Ende

22 of 39DDR3 SDRAMRev. 1.03 July 2009Unbuffered DIMM13.4 DIfferential Output Slew RateWith the reference load for timing measurements, output slew r

23 of 39DDR3 SDRAMRev. 1.03 July 2009Unbuffered DIMM14.0 IDD Specification DefinitionSymbol DescriptionIDD0 Operating One Bank Active-Precharge Curre

24 of 39DDR3 SDRAMRev. 1.03 July 2009Unbuffered DIMMa) Burst Length: BL8 fixed by MRS: set MR0 A[1,0]=00Bb) Output Buffer Enable: set MR1 A[12] = 0B;

25 of 39DDR3 SDRAMRev. 1.03 July 2009Unbuffered DIMM14.1 IDD SPEC TableM378B2873EH1 : 1GB(128Mx64) ModuleM378B5673EH1 : 2GB(256Mx64) ModuleSymbolCF8(

26 of 39DDR3 SDRAMRev. 1.03 July 2009Unbuffered DIMMM391B2873EH1: 1GB(128Mx72) ModuleM391B5673EH1: 2GB(256Mx72) ModuleSymbolCF8(DDR3-1066@CL=7)CH9(DD

27 of 39DDR3 SDRAMRev. 1.03 July 2009Unbuffered DIMM15.0 Input/Output Capacitance15.1 Non ECC UDIMM15.2 ECC UDIMMM378B2873EH1Parameter SymbolDDR3-106

28 of 39DDR3 SDRAMRev. 1.03 July 2009Unbuffered DIMM16.0 Electrical Characteristics and AC timing (0 °C<TCASE ≤95 °C, VDDQ = 1.5V ± 0.07

29 of 39DDR3 SDRAMRev. 1.03 July 2009Unbuffered DIMMDDR3-1333 Speed BinsSpeed DDR3-1333Units NoteCL-nRCD-nRP 9 -9 - 9Parameter Symbol min maxInternal

3 of 39DDR3 SDRAMRev. 1.03 July 2009Unbuffered DIMM14.0 IDD Specification Definition ...

30 of 39DDR3 SDRAMRev. 1.03 July 2009Unbuffered DIMMDDR3-1600 Speed BinsSpeed DDR3-1600Units NoteCL-nRCD-nRP 11-11-11Parameter Symbol min maxIntermal

31 of 39DDR3 SDRAMRev. 1.03 July 2009Unbuffered DIMM16.3.1 Speed Bin Table NotesAbsolute Specification (TOPER; VDDQ = VDD = 1.5V +/- 0.075 V);Note :1

32 of 39DDR3 SDRAMRev. 1.03 July 2009Unbuffered DIMM17.0 Timing Parameters by Speed GradeSpeed DDR3-1066 DDR3-1333DDR3-1600Units NoteParameter Symbol

33 of 39DDR3 SDRAMRev. 1.03 July 2009Unbuffered DIMMSpeed DDR3-1066 DDR3-1333DDR3-1600Units NoteParameter Symbol MIN MAX MIN MAX MIN MAXCommand and A

34 of 39DDR3 SDRAMRev. 1.03 July 2009Unbuffered DIMMSpeed DDR3-1066 DDR3-1333DDR3-1600Units NoteParameter Symbol MIN MAX MIN MAX MIN MAXPower Down Ti

35 of 39DDR3 SDRAMRev. 1.03 July 2009Unbuffered DIMM17.1 Jitter NotesSpecific Note a Unit ’tCK(avg)’ represents the actual tCK(avg) of the input cl

36 of 39DDR3 SDRAMRev. 1.03 July 2009Unbuffered DIMM17.2 Timing Parameter Notes1. Actual value dependant upon measurement level definitions which are

37 of 39DDR3 SDRAMRev. 1.03 July 2009Unbuffered DIMM133.35 ± 0.15Max 4.018.0 Physical Dimensions18.1 64Mbx16 based 64Mx64 Module (1 Rank)

38 of 39DDR3 SDRAMRev. 1.03 July 2009Unbuffered DIMM133.35 ± 0.15Max 4.018.2 128Mbx8 based 128Mx64/x72 Module (1 Rank) * Note : Toler

39 of 39DDR3 SDRAMRev. 1.03 July 2009Unbuffered DIMM18.3 128Mbx8 based 256Mx64/x72 Module (2 Ranks) * Note : Tolerances on all dimensi

4 of 39DDR3 SDRAMRev. 1.03 July 2009Unbuffered DIMMRevision HistoryRevision Month Year History1.0 December 2008 - First release1.01 January 2009

5 of 39DDR3 SDRAMRev. 1.03 July 2009Unbuffered DIMM1.0 DDR3 Registered DIMM Ordering InformationNote :- "##" - F8/H9/K0- F8 - 1066Mbps 7

6 of 39DDR3 SDRAMRev. 1.03 July 2009Unbuffered DIMM4.0 x64 DIMM Pin Configurations (Front side/Back Side)NC = No Connect; NF = No Function; NU = Not

7 of 39DDR3 SDRAMRev. 1.03 July 2009Unbuffered DIMM5.0 x72 DIMM Pin Configurations (Front side/Back side)NC = No Connect; NF = No Function; NU = Not

8 of 39DDR3 SDRAMRev. 1.03 July 2009Unbuffered DIMM6.0 Pin Description *The VDD and VDDQ pins are tied common to a single power-plane on these design

9 of 39DDR3 SDRAMRev. 1.03 July 2009Unbuffered DIMM8.0 Input/Output Functional DescriptionSymbol Type FunctionCK0-CK1CK0-CK1SSTLCK and CK are differe