Samsung M395T2863QZ4-CE660 Datasheet

Rev. 1.4 May 2009FBDIMM DDR2 SDRAM 1 of 42DDR2 Fully Buffered DIMM240pin FBDIMMs based on 1Gb Q-die(RoHS compliant)60FBGA with Lead-Free and Halogen-F

Rev. 1.4 May 2009FBDIMM DDR2 SDRAM 10 of 42Figure 9. Basic DRAM Write Data Transfers on FBDFigure 10. Simultaneous RD / WR Data TransfersACT1NOPNOPACT

Rev. 1.4 May 2009FBDIMM DDR2 SDRAM 11 of 422.7 Advanced Memory Buffer Block DiagramFigure 11. Advanced Memory Buffer Block DiagramAdvance Memory Buffe

Rev. 1.4 May 2009FBDIMM DDR2 SDRAM 12 of 422.8 InterfacesFigure 12 illustrates the Advanced Memory Buffer and all of its interfaces. They consist of t

Rev. 1.4 May 2009FBDIMM DDR2 SDRAM 13 of 423.3 FBD Channel LatencyFBD channel latency is measured from the time a read request is driven on the FBD ch

Rev. 1.4 May 2009FBDIMM DDR2 SDRAM 14 of 424.0 Pin Configuration[ Table 4 ] DDR2 240 Pin FBDIMM Configurations (Front side/Back side)RFU = Reserved Fu

Rev. 1.4 May 2009FBDIMM DDR2 SDRAM 15 of 42[ Table 5 ] Pin DescriptionPin Name Type Pin Description Pin NumbersSCK Input System Clock Input, positive

Rev. 1.4 May 2009FBDIMM DDR2 SDRAM 16 of 425.0 FBDIMM Functional Block Diagram5.1 1GB, 128Mx72 Module - M395T2863QZ4

Rev. 1.4 May 2009FBDIMM DDR2 SDRAM 17 of 425.2 2GB, 256Mx72 Module - M395T5663QZ4 (populated as 2 r

Rev. 1.4 May 2009FBDIMM DDR2 SDRAM 18 of 425.3 4GB, 512Mx72 Module - M395T5160 (populated as 2 ranks

Rev. 1.4 May 2009FBDIMM DDR2 SDRAM 19 of 425.4 4GB, 512Mx72 Module - M395T5163QZ4 (populated as 4

Rev. 1.4 May 2009FBDIMM DDR2 SDRAM 2 of 421.0 FEATURES ...

Rev. 1.4 May 2009FBDIMM DDR2 SDRAM 20 of 42DQS5DQS5DQS14DM/RDQSNU/RDQSCSDQS DQSDQ40DQ41DQ42DQ43DQ44DQ45DQ46DQ47I/O 0I/O 1I/O 2I/O 3I/O 4I/O 5I/O 6I/O

Rev. 1.4 May 2009FBDIMM DDR2 SDRAM 21 of 425.5 8GB, 1Gx72 Module - M395T1G60QJ4 (populated as 4 ranks of

Rev. 1.4 May 2009FBDIMM DDR2 SDRAM 22 of 42PN0-PN13PN0-PN13PS0-PS9PS0-PS9DQ0-DQ63CB0-CB7DQS0-DQS17DQS0-DQS17SCLSDARESETSCK/SCKSN0-SN13SN0-SN13SS0-SS9S

Rev. 1.4 May 2009FBDIMM DDR2 SDRAM 23 of 426.0 Electrical Characteristics[ Table 6 ] Absolute Maximum RatingsNote : 1. Stresses greater than those Iis

Rev. 1.4 May 2009FBDIMM DDR2 SDRAM 24 of 42[ Table 9 ] Power specification parameter and test conditionSymbol ConditionsPower SupplyUnitsIcc_Idle_0 Id

Rev. 1.4 May 2009FBDIMM DDR2 SDRAM 25 of 42[ Table 10 ] Power specification (Vdd Max = 1.900V, Vcc Max = 1.575V)(Vdd Max = 1.900V, Vcc Max = 1.575V)No

Rev. 1.4 May 2009FBDIMM DDR2 SDRAM 26 of 42(Vdd Max = 1.900V, Vcc Max = 1.575V)Note : 1. FBDIMM Power was calculated on the basis of DRAM and AMB Valu

Rev. 1.4 May 2009FBDIMM DDR2 SDRAM 27 of 42(Vdd Max = 1.900V, Vcc Max = 1.575V)Note : 1. FBDIMM Power was calculated on the basis of DRAM and AMB Valu

Rev. 1.4 May 2009FBDIMM DDR2 SDRAM 28 of 42[ Table 11 ] VTT Currents[ Table 12 ] Reference Clock Input SpecificationsNote :1. 133MHz for PC2-4200 and

Rev. 1.4 May 2009FBDIMM DDR2 SDRAM 29 of 42[ Table 13 ] Differential Transmitter Output SpecificationsParameter SymbolValuesUnits CommentsMIN MAXDiffe

Rev. 1.4 May 2009FBDIMM DDR2 SDRAM 3 of 42Revision HistoryRevision Month Year History1.0 March 2008 - Initial Spec. Release1.1 March 2008 - Added 4R

Rev. 1.4 May 2009FBDIMM DDR2 SDRAM 30 of 42[ Table 14 ] Differential Receiver Input SpecificationsNotes :1. Specified at the package pins into a timin

Rev. 1.4 May 2009FBDIMM DDR2 SDRAM 31 of 4211. The received differential signal must satisfy both this ratio as well as the absolute maximum AC peak t

Rev. 1.4 May 2009FBDIMM DDR2 SDRAM 32 of 427.0 CHANNEL INITIALIZATIONThis chapter defines the process of initializing the FBD channel. The FBD initial

Rev. 1.4 May 2009FBDIMM DDR2 SDRAM 33 of 428.0 Physical Dimensions :8.1 128Mbx8 based 128Mx72 Module (1 Rank)133.35126.85d5.17567 519.50b123a2x 3.252x

Rev. 1.4 May 2009FBDIMM DDR2 SDRAM 34 of 42Heat Spreader Design GuideUnits : Millimeters8.2 max1.27 ± 0.10Back3.0 max133.3530.35 ± 0.156712351

Rev. 1.4 May 2009FBDIMM DDR2 SDRAM 35 of 428.2 128Mbx8 based 256Mx72 Module (2 Ranks) M395T5663QZ43.802.505.01.50DETAIL a2.50 ± 0.20MAX 0.178DET

Rev. 1.4 May 2009FBDIMM DDR2 SDRAM 36 of 42Heat Spreader Design GuideUnits : Millimeters8.2 max1.27 ± 0.10Back3.0 max133.3530.35 ± 0.156712351

Rev. 1.4 May 2009FBDIMM DDR2 SDRAM 37 of 428.3 256Mbx4 based 512Mx72 Module (2 Ranks) M395T5160QZ4133.35126.85d18.802.05.17567 51c9.50bAMB123ae30

Rev. 1.4 May 2009FBDIMM DDR2 SDRAM 38 of 42Heat Spreader Design Guide133.3530.35 ± 0.1567 51123Units : Millimeters8.2 max1.27 ± 0.10Back3.0 max

Rev. 1.4 May 2009FBDIMM DDR2 SDRAM 39 of 428.4 128Mbx8 based 512Mx72 Module (4 Ranks) M395T5163QZ4133.35126.85d18.802.05.17567 51c9.50bAMB123ae3

Rev. 1.4 May 2009FBDIMM DDR2 SDRAM 4 of 421.0 Features[ Table 1 ] Ordering InformationNote :1. “Z” of Part number(11th digit) stands for Lead-Free and

Rev. 1.4 May 2009FBDIMM DDR2 SDRAM 40 of 42Heat Spreader Design GuideUnits : Millimeters8.2 max1.27 ± 0.10Back3.0 max133.3530.35 ± 0.156712351

Rev. 1.4 May 2009FBDIMM DDR2 SDRAM 41 of 428.5 256Mbx4 based 1Gx72 Module (4 Ranks) M395T1G60QJ4133.35126.85d18.802.05.17567 51c9.50bAMB123ae30.3

Rev. 1.4 May 2009FBDIMM DDR2 SDRAM 42 of 42Heat Spreader Design Guide133.3530.35 ± 0.1567 51123Units : Millimeters8.2 max1.27 ± 0.10Back3.0 max

Rev. 1.4 May 2009FBDIMM DDR2 SDRAM 5 of 422.0 FBDIMM Generals2.1 FBDIMM Operation OverviewFB-DIMM (Fully Buffered Dual in Line Memory Module) is desig

Rev. 1.4 May 2009FBDIMM DDR2 SDRAM 6 of 422.2 FBDIMM Channel Frequency ScalingThere are many frequency parameters including reference clock frequency,

Rev. 1.4 May 2009FBDIMM DDR2 SDRAM 7 of 422.3 FBDIMM Clocking SchemeIn FB-DIMM platform design, phase adjustment among reference clock inputs to each

Rev. 1.4 May 2009FBDIMM DDR2 SDRAM 8 of 42Figure 5. FBDIMM Command Encoding & SB FrameNote : The values in “ X” fields in non-reserved commands ab

Rev. 1.4 May 2009FBDIMM DDR2 SDRAM 9 of 422.6 Basic Timing DiagramFigure 7. Basic DRAM Read Data Transfers on FBDFigure 8. Back to Back DRAM Read Data