Samsung M471B5273BH1-CF8 Specifications

Rev. 1.03 June 2009 1 of 29DDR3 SDRAMUnbuffered SoDIMMDDR3 SDRAM Specification204pin Unbuffered SODIMM based on 2Gb B-die64-bit Non-ECC78FBGA with Lea

Rev. 1.03 June 2009 10 of 29DDR3 SDRAMUnbuffered SoDIMM8.0 Absolute Maximum Ratings8.1 Absolute Maximum DC RatingsNote :1. Stresses greater than those

Rev. 1.03 June 2009 11 of 29DDR3 SDRAMUnbuffered SoDIMM10.0 AC & DC Input Measurement Levels10.1 AC & DC Logic Input Levels for Single-ended S

Rev. 1.03 June 2009 12 of 29DDR3 SDRAMUnbuffered SoDIMM10.2 VREF Tolerances.The dc-tolerance limits and ac-noise limits for the reference voltages VRE

Rev. 1.03 June 2009 13 of 29DDR3 SDRAMUnbuffered SoDIMM10.3 AC and DC Logic Input Levels for Differential Signals10.3.1 Differential Signals Definitio

Rev. 1.03 June 2009 14 of 29DDR3 SDRAMUnbuffered SoDIMM10.3.3 Single-ended Requirements for Differential SignalsEach individual component of a differe

Rev. 1.03 June 2009 15 of 29DDR3 SDRAMUnbuffered SoDIMM10.3.4 Differential Input Cross Point VoltageTo guarantee tight setup and hold times as well as

Rev. 1.03 June 2009 16 of 29DDR3 SDRAMUnbuffered SoDIMM11.0 AC & DC Output Measurement Levels11.1 Single Ended AC and DC Output LevelsSingle Ended

Rev. 1.03 June 2009 17 of 29DDR3 SDRAMUnbuffered SoDIMM11.4 Differential Output Slew RateWith the reference load for timing measurements, output slew

Rev. 1.03 June 2009 18 of 29DDR3 SDRAMUnbuffered SoDIMM12.0 IDD specification definitionSymbol DescriptionIDD0 Operating One Bank Active-Precharge Cur

Rev. 1.03 June 2009 19 of 29DDR3 SDRAMUnbuffered SoDIMMa) Burst Length: BL8 fixed by MRS: set MR0 A[1,0]=00Bb) Output Buffer Enable: set MR1 A[12] = 0

Rev. 1.03 June 2009 2 of 29DDR3 SDRAMUnbuffered SoDIMM1.0 DDR3 Unbuffered SoDIMM Ordering Information ...

Rev. 1.03 June 2009 20 of 29DDR3 SDRAMUnbuffered SoDIMM12.1 IDD SPEC TableM471B5273BH1 : 4GB (512Mx64) Module13.0 Input/Output Capacitance13.1 2Rx16 1

Rev. 1.03 June 2009 21 of 29DDR3 SDRAMUnbuffered SoDIMM14.0 Electrical Characteristics and AC timing (0 °C<TCASE ≤95 °C, VDDQ = 1.5V ±

Rev. 1.03 June 2009 22 of 29DDR3 SDRAMUnbuffered SoDIMM14.3 Speed Bins and CL, tRCD, tRP, tRC and tRAS for corresponding Bin DDR3 SDRAM Spe

Rev. 1.03 June 2009 23 of 29DDR3 SDRAMUnbuffered SoDIMM14.3.1 Speed Bin Table NotesAbsolute Specification (TOPER; VDDQ = VDD = 1.5V +/- 0.075 V);Note

Rev. 1.03 June 2009 24 of 29DDR3 SDRAMUnbuffered SoDIMM15.0 Timing Parameters for DDR3-1066 and DDR3-1333Timing Parameters by Speed BinSpeed DDR3-1066

Rev. 1.03 June 2009 25 of 29DDR3 SDRAMUnbuffered SoDIMMTiming Parameters by Speed Bin (Cont.)Speed DDR3-1066 DDR3-1333Units NoteParameter Symbol MIN M

Rev. 1.03 June 2009 26 of 29DDR3 SDRAMUnbuffered SoDIMMTiming Parameters by Speed Bin (Cont.)Speed DDR3-1066 DDR3-1333Units NoteParameter Symbol MIN M

Rev. 1.03 June 2009 27 of 29DDR3 SDRAMUnbuffered SoDIMM15.1 Jitter NotesSpecific Note a Unit ’tCK(avg)’ represents the actual tCK(avg) of the input

Rev. 1.03 June 2009 28 of 29DDR3 SDRAMUnbuffered SoDIMM15.2 Timing Parameter Notes1. Actual value dependant upon measurement level definitions which

Rev. 1.03 June 2009 29 of 29DDR3 SDRAMUnbuffered SoDIMM16.0 Physical Dimensions :16.1 256Mbx8 based 512Mx64 Module (2 Ranks)The used device is 256M x8

Rev. 1.03 June 2009 3 of 29DDR3 SDRAMUnbuffered SoDIMM15.0 Timing Parameters for DDR3-1066 and DDR3-1333 ...

Rev. 1.03 June 2009 4 of 29DDR3 SDRAMUnbuffered SoDIMMRevision HistoryRevision Month Year History1.0 December 2008 - First Release1.01 February 2009

Rev. 1.03 June 2009 5 of 29DDR3 SDRAMUnbuffered SoDIMM1.0 DDR3 Unbuffered SoDIMM Ordering InformationNote :* ## : F8 / H9** F8 : 1066Mbps 7-7-7, H9

Rev. 1.03 June 2009 6 of 29DDR3 SDRAMUnbuffered SoDIMM4.0 x64 DIMM Pin Configurations (Front side/Back Side)Note :1. NC = No Connect, NU = Not Usable,

Rev. 1.03 June 2009 7 of 29DDR3 SDRAMUnbuffered SoDIMM5.0 Pin Description *The VDD and VDDQ pins are tied common to a single power-plane on these desi

Rev. 1.03 June 2009 8 of 29DDR3 SDRAMUnbuffered SoDIMM6.0 Input/Output Functional DescriptionSymbol Type FunctionCK0-CK1CK0-CK1InputThe system clock i

Rev. 1.03 June 2009 9 of 29DDR3 SDRAMUnbuffered SoDIMM7.0 Function Block Diagram:7.1 4GB, 512Mx64 Module (Populated as 2 ranks of x8 DDR3 SDRAMs)V7V8V