Samsung S3F401F User Manual

USER′S MANUAL S3F401F 16/32-BIT RISC MICROPROCESSOR November, 2007 REV 1.00 Confidential Proprietary of Samsung Electronics Co., Ltd Copyright ©

S3F401F_UM_REV1.00 MICROCONTROLLER vii Table of Contents (Continued) Chapter 10 SSP (Synchronous Serial Port) 1. Overview ...

S3F401F_UM_REV1.00 INVERTER MOTOR CONTROLLER (IMC) 6-21 4.13 SAW-TOOTH WAVE (IMMODE = 1) PWMSWAP = 0, PWMPOLU = 1 (High start), PWMPOLD = 0 (Low s

INVERTER MOTOR CONTROLLER (IMC) S3F401F_UM_REV1.00 6-22 4.14 SAW-TOOTH WAVE (IMMODE = 1) PWMSWAP = 1, PWMPOLU = 1 (High start), PWMPOLD = 0 (Low

S3F401F_UM_REV1.00 INVERTER MOTOR CONTROLLER (IMC) 6-23 4.15 SAW-TOOTH WAVE (IMMODE = 1) PWMSWAP = 0, PWMPOLU = 1 (High start), PWMPOLD = 1 (High

INVERTER MOTOR CONTROLLER (IMC) S3F401F_UM_REV1.00 6-24 4.16 SAW-TOOTH WAVE (IMMODE = 1) PWMSWAP = 1, PWMPOLU = 1 (High start), PWMPOLD = 1 (Hig

S3F401F_UM_REV1.00 INVERTER MOTOR CONTROLLER (IMC) 6-25 5. REGISTERS DESCRIPTION Table 6-1. IMC Special Function Registers Offset Address Regi

INVERTER MOTOR CONTROLLER (IMC) S3F401F_UM_REV1.00 6-26 Inverter Motor Control Register 0 IMCON0 (0x000) Access

S3F401F_UM_REV1.00 INVERTER MOTOR CONTROLLER (IMC) 6-27 Inverter Motor Control Register 0 (Continued) IMCON0 (0x000)

INVERTER MOTOR CONTROLLER (IMC) S3F401F_UM_REV1.00 6-28 Inverter Motor Control Register 0 (Continued) IMCON0 (0x000)

S3F401F_UM_REV1.00 INVERTER MOTOR CONTROLLER (IMC) 6-29 2) SYNCSEL = 01 TOPCMPThe compare registers(ADCCMPRx, ADCCMPFx, PACMPR/F, PBCMPR/F, PCCMP

INVERTER MOTOR CONTROLLER (IMC) S3F401F_UM_REV1.00 6-30 1) SYNCSEL = 00 TOPCMPThe compare registers are written in the rising time. The compare

viii S3F401F_UM_REV1.00 MICROCONTROLLER Table of Contents (Continued) Chapter 12 UART 1. Overview...

S3F401F_UM_REV1.00 INVERTER MOTOR CONTROLLER (IMC) 6-31 3) SYNCSEL = 10 TOPCMPThe compare registers are written in the rising time. The compare r

INVERTER MOTOR CONTROLLER (IMC) S3F401F_UM_REV1.00 6-32 Inverter Motor Control Register 1 IMCON1 (0x000) Access: Rea

S3F401F_UM_REV1.00 INVERTER MOTOR CONTROLLER (IMC) 6-33 Inverter Motor Control Register 1 (Continued) IMCON1 (0x000) A

INVERTER MOTOR CONTROLLER (IMC) S3F401F_UM_REV1.00 6-34 Inverter Motor Status Register IMSTATUS (0x008) Access: Read

S3F401F_UM_REV1.00 INVERTER MOTOR CONTROLLER (IMC) 6-35 ADC Start Signal Select Register ADCSTARETSEL (0x00C) Access: Read

INVERTER MOTOR CONTROLLER (IMC) S3F401F_UM_REV1.00 6-36 ADC Start Signal Select Register (Continued) ADCSTARETSEL (0x00C)

S3F401F_UM_REV1.00 INVERTER MOTOR CONTROLLER (IMC) 6-37 16-Bit Inverter Motor Counter Register IMCNT (0x010) Access: R

INVERTER MOTOR CONTROLLER (IMC) S3F401F_UM_REV1.00 6-38 16-Bit Top Compare Register TOPCMP (0x014) Access: Read/Writ

S3F401F_UM_REV1.00 INVERTER MOTOR CONTROLLER (IMC) 6-39 16-Bit Phase A Compare Register of Rising PACMPR (0x018) Acce

INVERTER MOTOR CONTROLLER (IMC) S3F401F_UM_REV1.00 6-40 16-Bit Phase B Compare Register of Rising PBCMPR (0x020) Ac

S3F401F_UM_REV1.00 MICROCONTROLLER ix List of Figures Figure Title Page Number Number 1-1 S3F401F Block Diagram...

S3F401F_UM_REV1.00 INVERTER MOTOR CONTROLLER (IMC) 6-41 16-Bit Phase C Compare Register of Rising PBCMPR (0x028) Acces

INVERTER MOTOR CONTROLLER (IMC) S3F401F_UM_REV1.00 6-42 16-Bit ADC Start Compare Register of Rising 0 ADCCMPR0 (0x030) Access: Rea

S3F401F_UM_REV1.00 INVERTER MOTOR CONTROLLER (IMC) 6-43 16-Bit ADC Start Compare Register of Rising 1 ADCCMPR1 (0x038) Access:

INVERTER MOTOR CONTROLLER (IMC) S3F401F_UM_REV1.00 6-44 16-Bit ADC Start Compare Register of Rising 2 ADCCMPR2DAT (0x040)

S3F401F_UM_REV1.00 INVERTER MOTOR CONTROLLER (IMC) 6-45 16-Bit Dead-time Compare Register DTCMPDAT (0x048) Access: Read/Write 31 30

S3F401F_UM_REV1.00 INTERRUPT CONTROLLER 7-1 7 INTERRUPT CONTROLLER 1. OVERVIEW Even if there are many

INTERRUPT CONTROLLER S3F401F_UM_REV1.00 7-2 CSPR.7(IRQ)==0, CSPR.6(FIQ)==0Global Interrupt Disable/Enable?INTMSKINTPNDInterrupt Source 89INTMODI

S3F401F_UM_REV1.00 INTERRUPT CONTROLLER 7-3 2. FUNCTIONAL DESCRIPTION The interrupt controller of S3F401F has the following features: ♦ The n

INTERRUPT CONTROLLER S3F401F_UM_REV1.00 7-4 2.2.3 Interrupt Mask Register (INTMSK) The interrupt mask register has interrupt mask bits for all i

S3F401F_UM_REV1.00 INTERRUPT CONTROLLER 7-5 2.3 INTERRUPT SOURCES In S3F401F, there are 90 interrupt sources being categorized into 9 groups from

x S3F401F_UM_REV1.00 MICROCONTROLLER List of Figures (Continued) Figure Title Page Number Number 10-1 SSP Block Diagram...

INTERRUPT CONTROLLER S3F401F_UM_REV1.00 7-6 Table 7-1. S3F401F Interrupt Sources (Continued) Num Group Source Name Description 32 C EOC ADC

S3F401F_UM_REV1.00 INTERRUPT CONTROLLER 7-7 Table 7-1. S3F401F Interrupt Sources Continued) Num Group Source Name Description 65 G URX0 UAR

INTERRUPT CONTROLLER S3F401F_UM_REV1.00 7-8 3. REGISTERS DESCRIPTION Table 7-2. Interrupt Controller Special Function Registers Offset Address

S3F401F_UM_REV1.00 INTERRUPT CONTROLLER 7-9 INTERRUPT MODE0 Register INTMOD0 (0x000) Access: Read/Write 31 30 29 28 27 26 25

INTERRUPT CONTROLLER S3F401F_UM_REV1.00 7-10 INTERRUPT MODE1 Register INTMOD1 (0x004) Access: Read/Write 31 30 29 28 27 26

S3F401F_UM_REV1.00 INTERRUPT CONTROLLER 7-11 INTERRUPT MODE2 Register INTMOD2 (0x008) Access: Read/Write 31 30 29 28 27 26 25

INTERRUPT CONTROLLER S3F401F_UM_REV1.00 7-12 INTERRUPT PENDING0 Register INTPND0 (0x00C) Access: Read/Write 31 30 29 28 2

S3F401F_UM_REV1.00 INTERRUPT CONTROLLER 7-13 INTERRUPT PENDING1 Register INTPND1 (0x010) Access: Read/Write 31 30 29 28 27 26

INTERRUPT CONTROLLER S3F401F_UM_REV1.00 7-14 INTERRUPT PENDING2 Register INTPND2 (0x014) Access: Read/Write 31 30 29 28 27 2

S3F401F_UM_REV1.00 INTERRUPT CONTROLLER 7-15 INTERRUPT MASK0 Register INTMSK0 (0x018) Access: Read/Write 31 30 29 28 27 26 25

S3F401F_UM_REV1.00 MICROCONTROLLER xi List of Tables Table Title Page Number Number 1-1 Pin Assignments − Pin Number Order...

INTERRUPT CONTROLLER S3F401F_UM_REV1.00 7-16 INTERRUPT MASK1 Register INTMSK1 (0x01C) Access: Read/Write 31 30 29 28 27

S3F401F_UM_REV1.00 INTERRUPT CONTROLLER 7-17 INTERRUPT MASK 2 Register INTMSK2 (0x020) Access: Read/Write 31 30 29 28 27 26 2

INTERRUPT CONTROLLER S3F401F_UM_REV1.00 7-18 INTERRUPT OFFSET Register for IRQ INTOFFSIRQ (0x024) Access: Read/Write 31 30 2

S3F401F_UM_REV1.00 INTERRUPT CONTROLLER 7-19 INTERRUPT OFFSET Register for FIQ INTOFFSFIQ (0x028) Access: Read Only 31 30 29

INTERRUPT CONTROLLER S3F401F_UM_REV1.00 7-20 INTERRUPT VECTOR ADDRESS Register for IRQ INTIRQADDR (0x028) Access: Read On

S3F401F_UM_REV1.00 INTERRUPT CONTROLLER 7-21 INTERRUPT VECTOR ADDRESS Register for FIQ INTFIQADDR (0x030) Access: Read O

INTERRUPT CONTROLLER S3F401F_UM_REV1.00 7-22 INTERRUPT VECTOR BASE ADDRESS Register INTVECBASE (0x034) Access: Read/Write 31

S3F401F_UM_REV1.00 INTERRUPT CONTROLLER 7-23 INTERRUPT CONTROL Register INTCNON (0x038) Access: Read/Write 31 30 29 28 27 26

INTERRUPT CONTROLLER S3F401F_UM_REV1.00 7-24 INTERRUPT PRIORITY Register INTPRI (0x03C) Access: Read/Writ

S3F401F_UM_REV1.00 INTERRUPT CONTROLLER 7-25 SOFTWARE INTERRUPT Register SWINT (0x040) Access: Read/Write 31 30

S3F401F_UM_REV1.00 PRODUCT OVERVIEW 1-1 1 PRODUCT OVERVIEW 1. OVERVIEW 1.1 INTRODUCTION Samsung's S3F401F 16/32-bit RISC microcontroller is

S3F401F_UM_REV1.00 I/O PORTS 8-1 8 I/O PORTS 1. OVERVIEW S3F401F has 65 multiplexed input/output po

I/O PORTS S3F401F_UM_REV1.00 8-2 2. S3F401F PORT CONFIGURATION OVERVIEW All three port groups have the identical function as shown in Table 8-1:

S3F401F_UM_REV1.00 I/O PORTS 8-3 3. I/O PORT CONTROL REGISTERS PORT CONTROL REGISTERS: PCON 0, PCON 1, PCON 2 In S3F401F, most pins are multiplex

I/O PORTS S3F401F_UM_REV1.00 8-4 4. REGISTERS DESCRIPTION Table 8-2. Port Control Special Function Registers Offset Address Register Descrip

S3F401F_UM_REV1.00 I/O PORTS 8-5 PORT0 Control Register PCON0H (0x000) Access: Read/Write 31 30 29 28 27 26 25 24 − −

I/O PORTS S3F401F_UM_REV1.00 8-6 PORT0 Control Register PCON0L (0x004) Access: Read/Write 31 30 29 28 27 26 25 24 P0.

S3F401F_UM_REV1.00 I/O PORTS 8-7 PORT0 Control Register (Continued) PCON0L (0x004) Access: Read/Write P0.5 PORT 0.5 00 =

I/O PORTS S3F401F_UM_REV1.00 8-8 PORT0 Control Register (Continued) PCON0L (0x004) Access: Read/Write P0.14 PORT 0.14 00

S3F401F_UM_REV1.00 I/O PORTS 8-9 PORT1 Control Register PCON1H (0x008) Access: Read/Write 31 30 29 28 27 26 25 24 − −

I/O PORTS S3F401F_UM_REV1.00 8-10 PORT1 Control Register (Continued) PCON1H (0x008) Access: Read/Write P1.20 PORT 1.20 0

PRODUCT OVERVIEW S3F401F_UM_REV1.00 1-2 2. FEATURESCPU • ARM7TDMI-S CPU Core • 32-bit RISC architecture Memory • 256 Kbytes Internal Program

S3F401F_UM_REV1.00 I/O PORTS 8-11 PORT1 Control Register (Continued) PCON1H (0x008) Access: Read/Write P1.27 PORT 1.27 00

I/O PORTS S3F401F_UM_REV1.00 8-12 PORT1 Control Register PCON1L (0x00C) Access: Read/Write 31 30 29 28 27 26 25 24 P

S3F401F_UM_REV1.00 I/O PORTS 8-13 PORT1 Control Register (Continued) PCON1L (0x00C) Access: Read/Write P1.4 PORT 1.4 00 =

I/O PORTS S3F401F_UM_REV1.00 8-14 PORT1 Control Register (Continued) PCON1L (0x00C) Access: Read/Write P1.10 PORT 1.10 0

S3F401F_UM_REV1.00 I/O PORTS 8-15 PORT2 Control Register PCON2 (0x010) Access: Read/Write 31 30 29 28 27 26 25 24 − − P2.14[29:

I/O PORTS S3F401F_UM_REV1.00 8-16 PORT2 Control Register (Continued) PCON2 (0x010) Access: Read/Write P2.5

S3F401F_UM_REV1.00 I/O PORTS 8-17 PORT0 Pull-Up Control Register PUR0 (0x014) Access: Read/Write 31 30 29 28 27 26 25 24 −

I/O PORTS S3F401F_UM_REV1.00 8-18 PORT1 Pull-Up Control Register PUR1 (0x018) Access: Read/Write 31 30 29 28 27 26 25 2

S3F401F_UM_REV1.00 I/O PORTS 8-19 PORT2 Pull-Up Control Register PUR2 (0x01C) Access: Read/Write 31 30 29 28

I/O PORTS S3F401F_UM_REV1.00 8-20 PORT0 Open-Drain Control Register OD0 (0x020) Access: Read/Write 31 30 2

S3F401F_UM_REV1.00 PRODUCT OVERVIEW 1-3 3. BLOCK DIAGRAM BT & WDTENC0/1Crystal orCeramicOscillatorAHBARM7TDMI-SCORESRAM20KBFLASH-ROM256KBI/

S3F401F_UM_REV1.00 I/O PORTS 8-21 PORT1 Open-Drain Control Register OD1 (0x024) Access: Read/Write 31 30 29

I/O PORTS S3F401F_UM_REV1.00 8-22 PORT2 Open-Drain Control Register OD2 (0x028) Access: Read/Write 31 30 29

S3F401F_UM_REV1.00 I/O PORTS 8-23 PORT0 Data Set Register PDATS0 (0x02C) Access: Write Only 31 30 29 28 27

I/O PORTS S3F401F_UM_REV1.00 8-24 PORT0 Data Reset Register PDATR0 (0x030) Access: Write Only 31 30 29 28

S3F401F_UM_REV1.00 I/O PORTS 8-25 PORT0 Data Status Register PDATSTAT0 (0x034) Access: Read Only 31 30 29

I/O PORTS S3F401F_UM_REV1.00 8-26 PORT1 Data Set Register PDATS1 (0x038) Access: Write Only 31 30 29 28 27 26

S3F401F_UM_REV1.00 I/O PORTS 8-27 PORT1 Data Reset Register PDATR1 (0x03C) Access: Write Only 31 30 29 28

I/O PORTS S3F401F_UM_REV1.00 8-28 PORT1 Data Status Register PDATSTAT1 (0x040) Access: Read Only 31 30 29

S3F401F_UM_REV1.00 I/O PORTS 8-29 PORT2 Data Set Register PDATS2 (0x044) Access: Write Only 31 30 29 28

I/O PORTS S3F401F_UM_REV1.00 8-30 PORT2 Data Reset Register PDATR2 (0x048) Access: Write Only 31 30 29

PRODUCT OVERVIEW S3F401F_UM_REV1.00 1-4 4. PIN ASSIGNMENTS S3F401F(100-QFP-1420C)PLLVSSIPVDDIO2PLLVDDCOREPLLVSSCOREPLLCAPXoutXinRTCKTMSTDITCKTDO

S3F401F_UM_REV1.00 I/O PORTS 8-31 PORT2 Data Status Register PDATSTAT2 (0x04C) Access: Read Only 31 30 2

I/O PORTS S3F401F_UM_REV1.00 8-32 External Interrupt Control Register EXTINTH (0x050) Access: Read/Write 31 30

S3F401F_UM_REV1.00 I/O PORTS 8-33 External Interrupt Control Register (Continued) EXTINTH (0x050) Access: Read/Write

I/O PORTS S3F401F_UM_REV1.00 8-34 External Interrupt Control Register EXTINTL (0x054) Access: Read/Wr

S3F401F_UM_REV1.00 I/O PORTS 8-35 External Interrupt Control Register (Continued) EXTINTL (0x054) Access: Read/Write

I/O PORTS S3F401F_UM_REV1.00 8-36 External Interrupt Filter Control Register EXTINTF0 (0x058) Access: Read/Write 31

S3F401F_UM_REV1.00 I/O PORTS 8-37 External Interrupt Filter Control Register (Continued) EXTINTF0 (0x058) Access: Read/Write EXTIN

I/O PORTS S3F401F_UM_REV1.00 8-38 External Interrupt Filter Control Register EXTINTF1 (0x05C) Access: Read/Write 31

S3F401F_UM_REV1.00 I/O PORTS 8-39 External Interrupt Filter Control Register (Continued) EXTINTF1 (0x05C) Access: Read/Write EXTINT

S3F401F_UM_REV1.00 CLOCK & POWER MANAGEMENT 9-1 9 CLOCK & POWER MANAGEMENT 1. OVERVIEW In the power control logic, S3F401F has various

S3F401F_UM_REV1.00 PRODUCT OVERVIEW 1-5 Table 1-1. Pin Assignments − Pin Number Order No. Pin Name Default Function State Flash Function1 P0.0

CLOCK & POWER MANAGEMENT S3F401F_UM_REV1.00 9-2 NoHIGHSPEEDNORMALSTOPYesIDLESWSWINTSWSWINTCKFAILCMRSTRESET(any kind)CM_PMSTAT.0== 0RST(*2)Y

S3F401F_UM_REV1.00 POWER MANAGEMENT 9-3 PCLKMUXFinFplloSCLKMUXMCLKICLKSYSCON.4:CLKSRCSYSCON.5:PLLONPLLPMSTAT.0:CMRSTSYSCON.9-.8:PCLKDIVSYSCON.

CLOCK & POWER MANAGEMENT S3F401F_UM_REV1.00 9-4 2. PHASE LOCKED LOOP 2.1 PLL The PLL within the clock generator is the circuit that synchron

S3F401F_UM_REV1.00 POWER MANAGEMENT 9-5 DividerPFinM[7:0]S[1:0]PWRDNPFDDividerMP[5:0]FvcoPUMPVCODividerSFrefFplloLoop FilterR1200pFCInternalPLL

CLOCK & POWER MANAGEMENT S3F401F_UM_REV1.00 9-6 3. MODE CHANGE 3.1 CHANGING CLOCK SPEED FROM NORMAL MODE TO HIGHSPEED MODE [NORMAL Æ HIGHSPE

S3F401F_UM_REV1.00 POWER MANAGEMENT 9-7 4. REGISTERS DESCRIPTION Table 9-1. Clock & Power Management Special Function Register Offset A

CLOCK & POWER MANAGEMENT S3F401F_UM_REV1.00 9-8 System Control Register SYSCON (0x000) Access: Read/Write 31 30 29

S3F401F_UM_REV1.00 POWER MANAGEMENT 9-9 System Control Register (Continued) SYSCON (0x000) Access: Read/Write Software Re

CLOCK & POWER MANAGEMENT S3F401F_UM_REV1.00 9-10 PLL Control Register PLLCON (0x004) Access: Read/Write 31 30 29 28 27 26

S3F401F_UM_REV1.00 POWER MANAGEMENT 9-11 Table 9-2. MDIV/PDIV/SDIV Allowed Values Fin (MHz) Fout(MHz) m p s MDIV PDIV SDIV 20 120 3 3 1

Important Notice The information in this publication has been carefully checked and is believed to be entirely accurate at the time of publication. S

PRODUCT OVERVIEW S3F401F_UM_REV1.00 1-6 Table 1-1. Pin Assignments − Pin Number Order (Continued) No. Pin Name Default Function State Flash F

CLOCK & POWER MANAGEMENT S3F401F_UM_REV1.00 9-12 PLL Locking Timer Register PLLLOCK (0x008) Access: Read/Write 31 30 29 28 27

S3F401F_UM_REV1.00 POWER MANAGEMENT 9-13 Power Management Status Register PMSTAT(0x00C) Access: Read Only 31 30 29 28 27 26 25 24

S3F401F_UM_REV1.00 SSP 10-1 10 SSP (SYNCHRONOUS SERIAL PORT) 1. OVERVIEW The S3F401F has two channels’

SSP S3F401F_UM_REV1.00 10-2 2. BLOCK DIAGRAM ClockPrescalerControlUnitTransmit ShifterTransmit FIFORegister(16 bit x 8)TransmitterReceive FIFOReg

S3F401F_UM_REV1.00 SSP 10-3 INTERFACERECEIVERCLK_PRECALERTRANSMITTERDMA_INT_CONBus Control SignalPRDATAPWDATAPADDRRXDTXDCONTROLUNITFSSCLK Figu

SSP S3F401F_UM_REV1.00 10-4 2.1.2 Clock Ratios In the slave mode of operation, the SSPCLK pin signal from the external master is double synchroniz

S3F401F_UM_REV1.00 SSP 10-5 2.1.3 Transmit and Receive Logic To configure the SSP as a master, clear the SSPCR1 register master or slave selectio

SSP S3F401F_UM_REV1.00 10-6 2.2 FRAME FORMAT The frame format is programmed through the FRF bits and the data word size through the DSS bits. Bit

S3F401F_UM_REV1.00 SSP 10-7 2.2.1 SSP format with SPO=0, SPH=0 Single and continuous transmission signal sequences for SSP format with SPO=0, SPH

SSP S3F401F_UM_REV1.00 10-8 In the case of a single word transmission, after all bits of the data word have been transferred, the SSPFSS line is r

S3F401F_UM_REV1.00 PRODUCT OVERVIEW 1-7 Table 1-1. Pin Assignments − Pin Number Order (Continued) No. Pin Name Default Function State Flash F

S3F401F_UM_REV1.00 SSP 10-9 2.2.3 SSP format with SPO=1, SPH=0 Single and continuous transmission signal sequences for SSP format with SPO=1, SPH

SSP S3F401F_UM_REV1.00 10-10 2.2.4 SSP Format with SPO=1, SPH=1 The transfer signal sequence for SSP format with SPO=1, SPH=1 is shown in below fi

S3F401F_UM_REV1.00 SSP 10-11 2.2.5 Examples of Master and Slave Configurations Below figures show how the PrimeCell SSP (PL022) peripheral can be

SSP S3F401F_UM_REV1.00 10-12 SPI MasterMOSIMISOSCKPL022 Configured as Slave0VPL022 Configured as SlaveSSPRXDSSPTXDSSPFSSSSPCLKSSVDD0VSSPRXDSSPTX

S3F401F_UM_REV1.00 SSP 10-13 2.3 INTERRUPT There are five interrupts generated by the SSP. Four of these are individual and maskable: Interrupt

SSP S3F401F_UM_REV1.00 10-14 3. REGISTERS DESCRIPTION Table 10-2. Clock & Power Management Special Function Register Offset Address Regis

S3F401F_UM_REV1.00 SSP 10-15 Control Register 0 SSPCR0 (0x000) Access: Read/Write 31 30 29 28 27 26 25 24 − − − − −

SSP S3F401F_UM_REV1.00 10-16 Control Register 1 SSPCR1 (0x004) Access: Read/Write 31 30 29 28 27 26 25 24 − − − − −

S3F401F_UM_REV1.00 SSP 10-17 Data Register SSPDR (0x008) Access: Read/Write 31 30 29 28 27 26 25 24 −

SSP S3F401F_UM_REV1.00 10-18 Status Register SSPSR (0x00C) Access: Read Only 31 30 29 28 27 26 25 24 − − − −

PRODUCT OVERVIEW S3F401F_UM_REV1.00 1-8 Table 1-1. Pin Assignments − Pin Number Order (Continued) No. Pin Name Default Function State Flash F

S3F401F_UM_REV1.00 SSP 10-19 Clock Prescale Register SSPCPSR (0x010) Access: Read/Write 31 30 29 28 27 26 25 24 − − − −

SSP S3F401F_UM_REV1.00 10-20 Interrupt Mask Set /Clear Register SSPIMSC (0x014) Access: Read/Write 31 30 29 28 27 26 25 24

S3F401F_UM_REV1.00 SSP 10-21 Raw Interrupt Status Register SSPRIS (0x018) Access: Read Only 31 30 29 28 27 26 25 24

SSP S3F401F_UM_REV1.00 10-22 Masked Interrupt Status Register SSPMIS (0x01C) Access: Read Only 31 30 29 28 2

S3F401F_UM_REV1.00 SSP 10-23 Interrupt Clear Register SSPICR (0x020) Access: Write Only 31 30 29 28 27 2

S3F401F_UM_REV1.00 TIMER 11-1 11 16-BIT TIMERS 1. OVERVIEW The S3F401F has six 16-bit timers: TIMER0,

TIMER S3F401F_UM_REV1.00 11-2 INTPNDINTMASKINT_TOFnNOTE1:The counter clear by match is occurred only in the interval mode.Timer n Buffer RegisterT

S3F401F_UM_REV1.00 TIMER 11-3 2. OPERATION DESCRIPTION 2.1 INTERVAL MODE OPERATION In interval mode, a match signal should be generated when the

TIMER S3F401F_UM_REV1.00 11-4 2.2 MATCH & OVERFLOW MODE OPERATION In this mode, a match signal can be generated when the counter value is iden

S3F401F_UM_REV1.00 TIMER 11-5 2.3 CAPTURE MODE OPERATION In capture mode, the timer can perform the capturing operation, which is that the counte

S3F401F_UM_REV1.00 PRODUCT OVERVIEW 1-9 5. PIN DESCRIPTIONS Table 1-2. S3F401F Pin Descriptions Module Pin Name Description I/O The MD[2:0] c

TIMER S3F401F_UM_REV1.00 11-6 2.4 PWM MODE OPERATION The timer can be used for generating the PWM (Pulse Width Modulation) signal. In this mode,

S3F401F_UM_REV1.00 TIMER 11-7 TCLKTPDAT9INT_OVERFLOWTnPWMINT_MATCHTDATTCNT012834567891001234567891001234567891001234567891001Period2 Figure 11-

TIMER S3F401F_UM_REV1.00 11-8 3. REGISTERS DESCRIPTION Table 11-1. TIMER Special Function Registers Offset Address Register Description R/

S3F401F_UM_REV1.00 TIMER 11-9 Timer Control Register TCON (0x000) Access: Read/Write 31 30 29

TIMER S3F401F_UM_REV1.00 11-10 Timer Control Register (Continued) TCON (0x000) Access: Read/Write

S3F401F_UM_REV1.00 TIMER 11-11 Timer Pre-Scale Register TPRE (0x004) Access: Read/Write 31 30 29 28 27 26 25 24 − − −

TIMER S3F401F_UM_REV1.00 11-12 Timer Data Register TDAT (0x008) Access: Read/Write 31 30 29 28 27 26

S3F401F_UM_REV1.00 TIMER 11-13 Timer Data Register for PWM TPDAT (0x00C) Access: Read/Write 31 30 29 28 2

TIMER S3F401F_UM_REV1.00 11-14 Timer Count Register TCNT (0x010) Access: Read Only 31 30 29

S3F401F_UM_REV1.00 UART 12-1 12 UART 1. OVERVIEW The S3F401F has two UART serial communication inte

PRODUCT OVERVIEW S3F401F_UM_REV1.00 1-10 Table 1-2. S3F401F Pin Descriptions (Continued) Module Pin Name Description I/O SDAT Serial Data p

UART S3F401F_UM_REV1.00 12-2 1.2 IrDA SIR BLOCK The IrDA SIR block contains an IrDA SIR protocol ENDEC. The SIR protocol ENDEC can be enabled for

S3F401F_UM_REV1.00 UART 12-3 1.3.2 IrDA SIR ENDEC block providing: : Programmable use of IrDA SIR or UART input/output : Support of IrDA SIR E

UART S3F401F_UM_REV1.00 12-4 1.5 VARIATIONS FROM THE 16C550 UART The UART varies from the industry-standard 16C550 UART device as follows: • Rece

S3F401F_UM_REV1.00 UART 12-5 2. BLOCK DIAGRAM Buad-rateGeneratorControlUnitTransmit ShifterTransmit FIFORegister(16 Byte)TransmitterReceive FIF

UART S3F401F_UM_REV1.00 12-6 3. FUNCTION DESCRIPTION 3.1 BAUD RATE GENERATOR The baud rate generator contains free-running counters that generate

S3F401F_UM_REV1.00 UART 12-7 3.2 TRANSMIT FIFO The transmit FIFO is an 8-bit wide, 16 location deep, FIFO memory buffer. CPU data written across

UART S3F401F_UM_REV1.00 12-8 3.6.2 Data Transmission or Reception Data received or transmitted is stored in two 16-byte FIFOs, though the receive

S3F401F_UM_REV1.00 UART 12-9 3.6.5 Disabling the FIFOs Additionally, you can disable the FIFOs. In this case, the transmit and receive sides of

UART S3F401F_UM_REV1.00 12-10 3.7.1 IrDA Data Modulation The IrDA SIR ENDEC comprises: • IrDA SIR transmit encoder • IrDA SIR receive decoder T

S3F401F_UM_REV1.00 UART 12-11 3.7.3 IrDA SIR Receive Decoder The SIR receive decoder demodulates the return-to-zero bit stream from the infrared

S3F401F_UM_REV1.00 PRODUCT OVERVIEW 1-11 Table 1-2. S3F401F Pin Descriptions (Continued) Module Pin Name Description I/O POWER VDDCORE[2:0] C

UART S3F401F_UM_REV1.00 12-12 3.8.1 UARTRXINTR The receive interrupt changes state when one of the following events occurs: • IFO MODE UARTRXINTR

S3F401F_UM_REV1.00 UART 12-13 3.8.3 UARTRTINTR The receive timeout interrupt is asserted when the receive FIFO is not empty, and no further data

UART S3F401F_UM_REV1.00 12-14 4. REGISTERS DESCRIPTION Table 12-1. UART Special Function Registers Offset Address Register Description R/W

S3F401F_UM_REV1.00 UART 12-15 UART Data Register UARTDR (0x000) Access: Read/Write 31 30 29 28 27 26 25 24 − − − − − − − − R/W-U R/W-U

UART S3F401F_UM_REV1.00 12-16 UART Data Register (Continued) UARTDR (0x000) Access: Read/Write OE_DR Overrun Error 0 = No overrun error during

S3F401F_UM_REV1.00 UART 12-17 Receive Status/Error Clear Register UARTRSR (0x004) Access: Read/Write 31 30 29 28 27 26 25 24 − − − − − −

UART S3F401F_UM_REV1.00 12-18 NOTES: 1. The received data character must be read first from UARTDR before reading the error status associated wit

S3F401F_UM_REV1.00 UART 12-19 UART Flag Register UARTFR (0x018) Access: Read Only 31 30 29 28 27 26 25 24 DBGEN − − −

UART S3F401F_UM_REV1.00 12-20 UART IrDA Low Counter Register UARTILPR (0x020) Access: Read/Write 31 30 29 28 27 26 25 24 −

S3F401F_UM_REV1.00 UART 12-21 UART Integer Baud Rate Register UARTIBRD (0x024) Access: Read/Write 31 30 29 28 27 26 25 24 − − − − − − −

PRODUCT OVERVIEW S3F401F_UM_REV1.00 1-12 6. MEMORY ADDRESS When the reset of S3F401F micro-controller is asserted, the ARM core is in boot mode

UART S3F401F_UM_REV1.00 12-22 UART Functional Baud Rate Register UARTFBRD (0x028) Access: Read/Write 31 30 29 28 27 26 25 24 − − − − − −

S3F401F_UM_REV1.00 UART 12-23 The maximum error using a 6-bit UARTTFBRD register = 1/64 x 100 = 1.56%. This occurs when m = 1, and the error is

UART S3F401F_UM_REV1.00 12-24 UART Line Control Clock Register UARTLCR_H (0x02C) Access: Read/Write 31 30 29 28 27 26 25 24 − − − − − − −

S3F401F_UM_REV1.00 UART 12-25 UART Line Control Clock Register (Continued) UARTLCR_H (0x02C) Access: Read/Write FEN Enable FIFO Mode 1: FIF

UART S3F401F_UM_REV1.00 12-26 UART Control Register UARTCR (0x030) Access: Read/Write 31 30 29 28 27 26 25 24 − − − − − − − − R/W-0 R/W-

S3F401F_UM_REV1.00 UART 12-27 UART Control Register (Continued) UARTCR (0x030) Access: Read/Write TXE Transmit Enable Bit 0: the transmit s

UART S3F401F_UM_REV1.00 12-28 UART Interrupt FIFO Level Select Register UARTIFLS (0x034) Access: Read/Write 31 30 29 28 27 26 25 24 − − − −

S3F401F_UM_REV1.00 UART 12-29 UART Interrupt Mask Set/Clear Register UARTIMSC (0x038) Access: Read/Write 31 30 29 28 27 26 25 24 − − − −

UART S3F401F_UM_REV1.00 12-30 UART Raw Interrupt Status Register UARTRIS (0x03C) Access: Read Only 31 30 29 28 27 26 25 24 − − − − − − −

S3F401F_UM_REV1.00 UART 12-31 UART Masked Interrupt Status Register UARTMIS (0x040) Access: Read Only 31 30 29 28 27 26 2

S3F401F_UM_REV1.00 PRODUCT OVERVIEW 1-13 Table 1-4. The Base Address of Peripheral Special Registers Peripheral Base Address CM 0xFF00_0000 BT/

UART S3F401F_UM_REV1.00 12-32 UART Interrupt Clear Register UARTICR (0x044) Access: Write Only 31 30 29 28 27 26 25 24 − −

S3F401F_UM_REV1.00 ELECTRICAL DATA 13-1 13 ELECTRICAL DATA 1. DC ELECTRICAL CHARACTERISTICS Table 13-1. Absolute Maximum Ratings (TA = 25°C) Par

ELECTRICAL DATA S3F401F_UM_REV1.00 13-2 Table 13-2. D.C. Electrical Characteristics (TA = −40°C to + 85°C, VDD = 3.3 ± 0.3V) Parameter Symbol

S3F401F_UM_REV1.00 ELECTRICAL DATA 13-3 Table 13-3. Timing Constants (TA = −40°C to + 85°C, VDD = 3.3 ± 0.3V) Parameter Symbol Min Typ Max

ELECTRICAL DATA S3F401F_UM_REV1.00 13-4 Table 13-5. Internal RC Oscillation Characteristics (TA = −40°C to + 85°C, VDD = 3.3 ± 0.3V) Oscillato

S3F401F_UM_REV1.00 ELECTRICAL DATA 13-5 Table 13-7. 12-bit ADC Electrical Characteristics (TA = −40°C to + 85°C, VDD = 3.3 ± 0.3V) Parameter Sy

ELECTRICAL DATA S3F401F_UM_REV1.00 13-6 Bottom OffsetTop OffsetActual Transfer CurveDigital(Reconstructed Signal)D0Analog InputAIIdeal Transfer

S3F401F_UM_REV1.00 ELECTRICAL DATA 13-7 100101110111011010001000LSB iDigital(Reconstructed Signal)D0Analog InputREFAIDLE(i) = LSBi - LSBi-1ILE

ELECTRICAL DATA S3F401F_UM_REV1.00 13-8 Table 13-8. AC Electrical Characteristics for Internal Flash ROM (TA = −40°C to + 85°C, VDD = 3.3 ± 0.

S3F401F_UM_REV1.00 MECHANICAL DATA 14-1 14 MECHANICAL DATA 1. OVERVIEW The S3F401F is available in a 100-QFP-1420 package. 100-QFP-1420C#10020.00

S3F401F_UM_REV1.00 A/D CONVERTER 2-1 2 A/D CONVERTER 1. OVERVIEW The S3F401F has a 12-bit ADC. It con

MECHANICAL DATA S3F401F_UM_REV1.00 14-2 NOTES

A/D CONVERTER S3F401F_UM_REV1.00 2-2 2. BLOCK DIAGRAM ADCCON.15-.12: SHA1SELAIN1AIN0AIN13AIN14ADCCON.19-.16:SHA2SELAIN1AIN0AIN13AIN14ADCCON.23-.

NOTIFICATION OF REVISIONS ORIGINATOR: Samsung Electronics, LSI Development Group, Gi-Heung, South Korea PRODUCT NAME: S3F401F Microcontroller DO

S3F401F_UM_REV1.00 A/D CONVERTER 2-3 3. A/D CONVERTER OPERATION 3.1 FUNCTION DESCRIPTION ADC has 3-analog input channels, SHA1, SHA2 and SHA3.

A/D CONVERTER S3F401F_UM_REV1.00 2-4 3.1.2 A/D Conversion 3.1.2.1 The Sampling Mode S3F401F′s ADC can get the result of maximum 3 converted digi

S3F401F_UM_REV1.00 A/D CONVERTER 2-5 3.1.3 Standby Mode Standby mode is activated when ADCCON.1 is set to '0'. In this mode, A/D conv

A/D CONVERTER S3F401F_UM_REV1.00 2-6 ADC EnableWhich Sampling Mode?SoftwareADC STARTADCTRGConversion SHA1 Conversion SHA1Conversion SHA2readADC

S3F401F_UM_REV1.00 A/D CONVERTER 2-7 4. REGISTERS DESCRIPTION Table 2-2. ADC Control Special Function Registers Offset Address Register Des

A/D CONVERTER S3F401F_UM_REV1.00 2-8 ADC Control Register ADCCON (0x000) Access: Read/Write 31 30 29 28 27 26 25 2

S3F401F_UM_REV1.00 A/D CONVERTER 2-9 ADC Control Register (Continued) ADCCON (0x000) Access: Read/Write MODESEL AD

A/D CONVERTER S3F401F_UM_REV1.00 2-10 ADC Status Register ADCSTATUS (0x004) Access: Read Only 31 30 29 28 27 26 25

S3F401F_UM_REV1.00 A/D CONVERTER 2-11 ADC Converter Data1 Register ADCRESULT1 (0x008) Access: Read Only 31 30 29 2

A/D CONVERTER S3F401F_UM_REV1.00 2-12 ADC Converter Data2 Register ADCRESULT2 (0x00C) Access: Read Only 31 30 29 28

REVISION HISTORY Revision Description of Change Author(s) Date Juil Kim 0.00 Preliminary Spec for internal release only. Younghee Jin Nov, 2006 1.

S3F401F_UM_REV1.00 A/D CONVERTER 2-13 ADC Converter Data3 Register ADCRESULT3 (0x010) Access: Read Only 31 30 29 2

S3F401F_UM_REV1.00 BASIC TIMER & WDT 3-1 3 BASIC TIMER & WATCHDOG TIMER 1. OVERVIEW Basic Timer

BASIC TIMER & WDT S3F401F_UM_REV1.00 3-2 2. FUNCTION DESCRIPTION 2.1 INTERVAL TIMER FUNCTION The primary function of Basic Timer is to measu

S3F401F_UM_REV1.00 BASIC TIMER & WDT 3-3 2.2 WATCHDOG TIMER OPERATION The Basic Timer can also be used as a "Watch-Dog" Timer to re

BASIC TIMER & WDT S3F401F_UM_REV1.00 3-4 2.3 TIMER DURATION 2.3.1 Basic Timer Duration The Basic Timer Counter, BTCNT, can be used to specif

S3F401F_UM_REV1.00 BASIC TIMER & WDT 3-5 2.4 WATCH DOG TIMER DURATION The Watch-Dog Timer Counter, WTCNT, can be used to specify the time-out

BASIC TIMER & WDT S3F401F_UM_REV1.00 3-6 3. REGISTERS DESCRIPTION Table 3-1. Basic timer & WDT Special Function Registers Offset Addre

S3F401F_UM_REV1.00 BASIC TIMER & WDT 3-7 Basic Timer Control Register BTCON (0x000) Access: Read/Write 31 30 29 28 27

BASIC TIMER & WDT S3F401F_UM_REV1.00 3-8 Basic Timer Count Register BTCNT (0x004) Access: Read Only 31 30 29

S3F401F_UM_REV1.00 ENCODER COUNTER 4-1 4 ENCODER COUNTER 1. OVERVIEW The S3F401F has two encoder counter blocks

REVISION DESCRIPTIONS (REV 1.00) Chapter Chapter Name Page Subjects (Major changes comparing with last version) − − −

ENCODER COUNTER S3F401F_UM_REV1.00 4-2 PHASEAPHASEBPHASEZENCCON1.9: PAENENCCON1.1: PBENPACLKPBCLK16-bit Comparator16-bit ComparatorENCCON0.7: PZ

S3F401F_UM_REV1.00 ENCODER COUNTER 4-3 2. FUNCTION DESCRIPTION PHASEAPHASEB+1 +1 +1 +1 +1 +1 +1 +1 +1 +1 +1 -1 -1 -1 -1 -1PCNTENCSTATUS.0 = DIRE

ENCODER COUNTER S3F401F_UM_REV1.00 4-4 3. REGISTERS DESCRIPTION Table 4-1. ENC Special Function Registers Offset Address Register Descriptio

S3F401F_UM_REV1.00 ENCODER COUNTER 4-5 Encoder Counter Control Register 0 ENCCON0 (0x000) Access: Read/Write 31 3

ENCODER COUNTER S3F401F_UM_REV1.00 4-6 Encoder Counter Control Register 0 (Continued) ENCCON0 (0x000) Access: Read/W

S3F401F_UM_REV1.00 ENCODER COUNTER 4-7 Encoder Counter Status Register ENCSTATUS (0x008) Access: Read/Write 31 30 29 28

ENCODER COUNTER S3F401F_UM_REV1.00 4-8 Encoder Counter Status Register (Continued) ENCSTATUS (0x008) Access: Read/Write OFPCNT Overflow

S3F401F_UM_REV1.00 ENCODER COUNTER 4-9 16 Bit Position Counter Register PCNT (0x00C) Access: Read/Write 3

ENCODER COUNTER S3F401F_UM_REV1.00 4-10 16 Bit Speed Counter Register SCNT (0x014) Access: Read/Write 31

S3F401F_UM_REV1.00 ENCODER COUNTER 4-11 16 Bit Phase A Capture Counter Register PACNT (0x01C) Access: Read/Write 31 30 29

S3F401F_UM_REV1.00 MICROCONTROLLER iii Table of Contents Chapter 1 Product Overview 1. Overview ...

ENCODER COUNTER S3F401F_UM_REV1.00 4-12 16 Bit t Phase B Capture Counter Register PBCNT (0x024) Access: Read/W

S3F401F_UM_REV1.00 INTERNAL FLASH ROM 5-1 5 INTERNAL FLASH ROM 1. OVERVIEW The S3F401F has an on-chip flash ROM, internally. The memory flash s

INTERNAL FLASH ROM S3F401F_UM_REV1.00 5-2 3. FLASH CONFIGURATION 3.1 FLASH ROM CONFIGURATION The 256KBytes Flash ROM consists of 256 sectors. Eac

S3F401F_UM_REV1.00 INTERNAL FLASH ROM 5-3 4. PROGRAMMING MODES The Flash Memory Controller supports two kinds of program mode: ♦ User program m

INTERNAL FLASH ROM S3F401F_UM_REV1.00 5-4 4.2 NORMAL PROGRAM +START; Address set; Data set; Key value

S3F401F_UM_REV1.00 INTERNAL FLASH ROM 5-5 4.3 OPTION PROGRAM START; Protection/Smart option register address set; Option Bit set; Key value se

INTERNAL FLASH ROM S3F401F_UM_REV1.00 5-6 4.4 SECTOR ERASE ; Address set; Data set; Key value set whenenver starts; Program command select &

S3F401F_UM_REV1.00 INTERNAL FLASH ROM 5-7 4.5 CHIP ERASE FLOWCHART +; Key value set whenenver starts;

INTERNAL FLASH ROM S3F401F_UM_REV1.00 5-8 4.6 TOOL PROGRAM MODE The tool program mode is the flash memory program mode, which uses an equipment t

S3F401F_UM_REV1.00 INTERNAL FLASH ROM 5-9 5. DATA PROTECTION The data programmed in flash memory need to be protected. For this situation, the I

iv S3F401F_UM_REV1.00 MICROCONTROLLER Table of Contents (Continued) Chapter 4 Encoder Counter 1. Overview...

INTERNAL FLASH ROM S3F401F_UM_REV1.00 5-10 5.2 JTAG INTERFACE PROTECTION BIT 8 This Bit is used for JTAG Access enable or disable (If chip design

S3F401F_UM_REV1.00 INTERNAL FLASH ROM 5-11 Table 5-4. Hardware Protection Area FMDATA[15:0] Hardware Protection Area Sector Protected Area Add

INTERNAL FLASH ROM S3F401F_UM_REV1.00 5-12 6. REGISTERS DESCRIPTION Table 5-5. Internal Flash Special Function Registers Offset Address Regist

S3F401F_UM_REV1.00 INTERNAL FLASH ROM 5-13 Flash Memory Key Register FMKEY (0x000) Access: Write Only 31 30 29 28 27 2

INTERNAL FLASH ROM S3F401F_UM_REV1.00 5-14 Flash Memory Address Register FMADDR (0x004) Access: Read/Write 31 30 29 28 27

S3F401F_UM_REV1.00 INTERNAL FLASH ROM 5-15 Flash Memory Data Register FMDATA (0x008) Access: Read/Write 31 30 29 28 27 2

INTERNAL FLASH ROM S3F401F_UM_REV1.00 5-16 Flash Memory Control Register FMUCON (0x00C) Access: Read/Write 31 30 29 28 2

S3F401F_UM_REV1.00 INTERNAL FLASH ROM 5-17 Flash Memory Control Register (Continued) FMUCON (0x00C) Access: Read/Write UST

INTERNAL FLASH ROM S3F401F_UM_REV1.00 5-18 Smart Option Bits Read Register FSO (0x010) Access: Read Only 31 30 29

S3F401F_UM_REV1.00 INTERNAL FLASH ROM 5-19 Protection Option Bits Read Register FPO (0x014) Access: Read Only 31

S3F401F_UM_REV1.00 MICROCONTROLLER v Table of Contents (Continued) Chapter 6 Inverter Motor Controller (IMC) 1. Overview ...

S3F401F_UM_REV1.00 INVERTER MOTOR CONTROLLER (IMC) 6-1 6 INVERTER MOTOR CONTROLLER (IMC) 1. OVERVIEW This inverte

INVERTER MOTOR CONTROLLER (IMC) S3F401F_UM_REV1.00 6-2 2. BLOCK DIAGRAM ClearClearIMCON0.7-.6:ELESPWMOFFIMCLKADC Start TriggerADCSTARTSEL.7-.0I

S3F401F_UM_REV1.00 INVERTER MOTOR CONTROLLER (IMC) 6-3 3. FUNCTION DESCRIPTION 3.1 TRI-ANGULAR WAVE INTERRUPTPWMxU0PWMxD0can be used as ADC Trigg

INVERTER MOTOR CONTROLLER (IMC) S3F401F_UM_REV1.00 6-4 3.2 SAW-TOOTH WAVE INTERRUPTPWMxU0PWMxD0can be used as ADC Trigger Signal2367ADCCMPR0=6

S3F401F_UM_REV1.00 INVERTER MOTOR CONTROLLER (IMC) 6-5 4. PHASE SIGNAL GENERATION 4.1 TRI-ANGULAR WAVE (IMMODE = 0) PWMSWAP = 0, PWMPOLU = 0 (Low

INVERTER MOTOR CONTROLLER (IMC) S3F401F_UM_REV1.00 6-6 For 100% duty of upside, the rising/falling compare register must be set to ‘0’. For 0% d

S3F401F_UM_REV1.00 INVERTER MOTOR CONTROLLER (IMC) 6-7 4.2 TRI-ANGULAR WAVE (IMMODE = 0) PWMSWAP = 1, PWMPOLU = 0 (Low start), PWMPOLD = 1 (High

INVERTER MOTOR CONTROLLER (IMC) S3F401F_UM_REV1.00 6-8 The signal of PWM is described in the below picture. (Assumption: Duration of deadtime is

S3F401F_UM_REV1.00 INVERTER MOTOR CONTROLLER (IMC) 6-9 4.3 TRI-ANGULAR WAVE (IMMODE = 0) PWMSWAP = 0, PWMPOLU = 0 (Low start), PWMPOLD = 0 (Low s

INVERTER MOTOR CONTROLLER (IMC) S3F401F_UM_REV1.00 6-10 4.4 TRI-ANGULAR WAVE (IMMODE = 0) PWMSWAP = 1, PWMPOLU = 0 (Low start), PWMPOLD = 0 (Lo

vi S3F401F_UM_REV1.00 MICROCONTROLLER Table of Contents (Continued) Chapter 8 I/O Ports 1. Overview...

S3F401F_UM_REV1.00 INVERTER MOTOR CONTROLLER (IMC) 6-11 4.5 TRI-ANGULAR WAVE (IMMODE = 0) PWMSWAP = 0, PWMPOLU = 1 (High start), PWMPOLD = 0 (Low

INVERTER MOTOR CONTROLLER (IMC) S3F401F_UM_REV1.00 6-12 The signal of PWM is described in the below picture. (Assumption: Duration of dead-time

S3F401F_UM_REV1.00 INVERTER MOTOR CONTROLLER (IMC) 6-13 4.6 TRI-ANGULAR WAVE (IMMODE = 0) PWMSWAP = 1, PWMPOLU = 1 (High start), PWMPOLD = 0 (Low

INVERTER MOTOR CONTROLLER (IMC) S3F401F_UM_REV1.00 6-14 4.7 TRI-ANGULAR WAVE (IMMODE = 0) PWMSWAP = 0, PWMPOLU = 1 (High start), PWMPOLD = 1 (H

S3F401F_UM_REV1.00 INVERTER MOTOR CONTROLLER (IMC) 6-15 4.8 TRI-ANGULAR WAVE (IMMODE = 0) PWMSWAP = 1, PWMPOLU = 1 (High start), PWMPOLD = 1 (Hig

INVERTER MOTOR CONTROLLER (IMC) S3F401F_UM_REV1.00 6-16 4.9 SAW-TOOTH WAVE (IMMODE = 1) PWMSWAP = 0, PWMPOLU = 0 (Low start), PWMPOLD = 1 (High

S3F401F_UM_REV1.00 INVERTER MOTOR CONTROLLER (IMC) 6-17 Upside 0% dutysettingUpside 50% dutysettingUpside 100% dutysettingUpside 50% dutysettingU

INVERTER MOTOR CONTROLLER (IMC) S3F401F_UM_REV1.00 6-18 4.10 SAW-TOOTH WAVE (IMMODE = 1) PWMSWAP = 1, PWMPOLU = 0 (Low start), PWMPOLD = 1 (High

S3F401F_UM_REV1.00 INVERTER MOTOR CONTROLLER (IMC) 6-19 4.11 SAW-TOOTH WAVE (IMMODE = 1) PWMSWAP = 0, PWMPOLU = 0 (Low start), PWMPOLD = 0 (Low st

INVERTER MOTOR CONTROLLER (IMC) S3F401F_UM_REV1.00 6-20 4.12 SAW-TOOTH WAVE (IMMODE = 1) PWMSWAP = 1, PWMPOLU = 0 (Low start), PWMPOLD = 0 (Low