Samsung S3C2440A User Manual download pdf (Page 171)

MEMORY CONTROLLER S3C2440A RISC MICROPROCESSOR

nXBREQ/nXBACK Pin Operation

If nXBREQ is asserted, the S3C2440A will respond by lowering nXBACK. If nXBACK=L, the address/data bus and

memory control signals are in Hi-Z state as shown in Table 1-1. After nXBREQ is de-asserted, the nXBACK will

also be de-asserted.

SCKE, A[24:0]

D[31:0], nGCS

Figure 5-3. S3C2440A nXBREQ/nXBACK Timing Diagram

Samsung S3C2440A User Manual Page 171