Samsung S3C2440A User Manual Page 260
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I/O PORTS S3C2440A RISC MICROPROCESSOR
9-14
GPDDAT Bit Description
GPD[15:0] [15:0] When the port is configured as input port, the corresponding bit is the pin
state. When the port is configured as output port, the pin state is the same as
the corresponding bit. When the port is configured as functional pin, the
undefined value will be read.
GPDUP Bit Description
GPD[15:0] [15:0] 0: the pull up function attached to to the corresponding port pin is enabled.
1: the pull up function is disabled.
- S3C2440A 1
- 1 PRODUCT OVERVIEW 2
- FEATURES 3
- FEATURES (Continued) 4
- PIN ASSIGNMENTS 7
- VD20/GPD12 T6 VDDiarm 10
- @nRESET4 OSCin 20
- 2 PROGRAMMER'S MODEL 42
- 3 ARM INSTRUCTION SET 58
- THE CONDITION FIELD 61
- BRANCH AND EXCHANGE (BX) 62
- [24] Link bit 64
- DATA PROCESSING 66
- [6:5] Shift type 69
- [11:7] Shift amount 69
- [11:8] Shift register 69
- PSR TRANSFER (MRS, MSR) 75
- Figure 3-11. PSR Transfer 76
- [19:16] Destination Register 79
- [20] Set Condition Code 79
- [21] Accumulate 79
- ARM920T pipelining 89
- [6][5] S H 91
- [3:0] Source Register 104
- [15:12] Destination Register 104
- [19:16] Base Register 104
- [22] Byte/Word Bit 104
- [31:28] Condition Field 104
- SOFTWARE INTERRUPT (SWI) 106
- • • • 107
- [11:8] Coprocessor Number 110
- 1 = Up: add offset to base 110
- for single data transfers 111
- <expression> bytes 112
- 4 THUMB INSTRUCTION SET 122
- FORMAT SUMMARY 123
- [2:0] Destination Register 126
- [5:3] Source Register 126
- [10:6] Immediate Vale 126
- [12:11] Opcode 126
- FORMAT 2: ADD/SUBTRACT 128
- [7:0] Immediate Vale 130
- FORMAT 4: ALU OPERATIONS 132
- [6] Hi Operand Flag 2 134
- [7] Hi Operand Flag 1 134
- [9:8] Opcode 134
- FORMAT 6: PC-RELATIVE LOAD 137
- [10] Byte/Word Flag 139
- [10] Sign-Extended Flag 141
- [11] Load/Store Flag 143
- INSTRUCTION CYCLE TIMES 144
- [5:3] Base Register 145
- [10:6] Immediate Value 145
- 255 words, 1020 147
- FORMAT 12: LOAD ADDRESS 149
- 1 = Offset is negative 151
- [7:0] Register List 152
- [8] PC/LR Bit 152
- [11] Load/Store Bit 152
- [10:8] Base Register 154
- [7:0] 8-bit Signed Immediate 155
- [11:8] Condition 155
- [7:0] Comment Field 157
- EXAMPLES 158
- [11] Low/High Offset Bit 159
- 1 = Offset low 159
- INSTRUCTION SET EXAMPLES 161
- 5 MEMORY CONTROLLER 166
- FUNCTION DESCRIPTION 168
- 5-10 175
- DEC.13, 2002 176
- PROGRAMMABLE ACCESS CYCLE 176
- 5-12 177
- 5-13 178
- 5-15 180
- 5-16 181
- 5-17 182
- 5-18 183
- 5-19 184
- 5-20 185
- 6 NAND FLASH CONTORLLER 186
- SOFTWARE MODE 190
- CLOCK & POWER MANAGEMENT 208
- FUNCTIONAL DESCRIPTION 209
- HDIVN PDIVN 210
- Management 217
- NORMAL Mode 219
- IDLE Mode 219
- SLOW Mode (Non-PLL Mode) 219
- SLEEP Mode 222
- Output Low 223
- Figure 7-12. SLEEP Mode 224
- Entering IDLE Mode 225
- PLL On/Off 225
- ADC Power Down 226
- OVERVIEW 233
- DMA REQUEST SOURCES 234
- DMA OPERATION 234
- Read Write 235
- Transfer Size 237
- DMA SPECIAL REGISTERS 239
- 8-10 242
- 8-11 243
- 8-12 244
- 8-13 245
- 8-14 246
- 9 I/O PORTS 247
- PORT CONTROL DESCRIPTIONS 253
- I/O PORT CONTROL REGISTER 254
- 9-10 256
- 9-11 257
- 9-12 258
- 9-13 259
- 9-14 260
- 9-15 261
- 9-16 262
- 9-17 263
- 9-18 264
- 9-19 265
- 9-20 266
- 9-21 267
- 9-22 268
- 9-23 269
- 9-24 270
- 9-25 271
- DCLKnDIV + 1 272
- DCLKnCMP + 1 272
- 9-27 273
- 9-28 274
- 9-29 275
- 9-30 276
- 9-31 277
- 9-32 278
- 9-33 279
- 9-34 280
- 9-35 281
- 9-36 282
- 9-37 283
- 9-38 284
- 10 PWM TIMER 285
- 10-2 286
- PWM TIMER OPERATION 287
- 10-4 288
- 10-5 289
- 50 110 4040 6020 290
- 10-7 291
- Inverter off 292
- Inverter on 292
- 10-9 293
- PWM TIMER CONTROL REGISTERS 295
- 10-12 296
- 10-13 297
- 10-14 298
- 10-15 299
- 10-16 300
- 10-17 301
- 10-18 302
- 10-19 303
- 10-20 304
- 11 UART 305
- BLOCK DIAGRAM 306
- 11-3 307
- 11-4 308
- 11-5 309
- 11-6 310
- 11-7 311
- 11-8 312
- 11-9 313
- UART SPECIAL REGISTERS 314
- 11-11 315
- 11-15 319
- 11-16 320
- 11-17 321
- 11-18 322
- Delta CTS 323
- Read_UMSTAT 323
- 11-21 325
- 11-22 326
- 12 USB HOST CONTROLLER 327
- 12-2 328
- 13 USB DEVICE CONTROLLER 329
- NON INDEXED REGISTERS 331
- 13-4 332
- 13-5 333
- 13-6 334
- 13-7 335
- 13-8 336
- 13-9 337
- 13-10 338
- 13-11 339
- 13-12 340
- 13-13 341
- 13-14 342
- 13-15 343
- 13-16 344
- 13-17 345
- 13-18 346
- 13-19 347
- 13-20 348
- 13-21 349
- 13-22 350
- 14 INTERRUPT CONTROLLER 351
- 14-2 352
- 14-3 353
- 14-4 354
- 14-5 355
- 14-6 356
- 14-7 357
- 14-8 358
- 14-9 359
- 14-10 360
- 14-11 361
- 14-12 362
- 14-13 363
- 14-14 364
- 14-15 365
- 14-16 366
- 14-17 367
- 14-18 368
- 15 LCD CONTROLLER 369
- STN LCD CONTROLLER OPERATION 372
- , B = 2 372
- LCD Panel 377
- 15-10 378
- 15-11 379
- 15-12 380
- 15-13 381
- 15-14 382
- Full Frame Timing(MMODE = 0) 383
- TFT LCD CONTROLLER OPERATION 384
- P1 P2 P3 P4 P5 385
- P6 P7 P8 P10 P11 P12P9 387
- 15-20 388
- 15-22 390
- 15-23 391
- 15-24 392
- 15-25 393
- 15-26 394
- 15-27 395
- 15-28 396
- 15-29 397
- 15-30 398
- 15-31 399
- 15-32 400
- 15-34 402
- 15-35 403
- 15-36 404
- 15-37 405
- 15-38 406
- 15-39 407
- 15-40 408
- 15-41 409
- 15-42 410
- 15-43 411
- 15-44 412
- 16-2 414
- FUNCTION DESCRIPTIONS 415
- X-Tal CLK 416
- 16-5 417
- 16-6 418
- 16-7 419
- 16-8 420
- 16-9 421
- 16-10 422
- 17 REAL TIME CLOCK 423
- 17-2 424
- 17-3 425
- 17-5 427
- 17-6 428
- 17-7 429
- 17-8 430
- 17-9 431
- 17-10 432
- 18 WATCHDOG TIMER 433
- 18-2 434
- 18-3 435
- 01 : 32 435
- 18-4 436
- 19 MMC/SD/SDIO Controller 437
- SD OPERATION 438
- SDIO OPERATION 439
- SDI SPECIAL REGISTERS 440
- 19-5 441
- 19-6 442
- 19-7 443
- 19-8 444
- 19-9 445
- 19-10 446
- 19-11 447
- Initial Value 447
- 19-12 448
- 20 IIC-BUS INTERFACE 449
- Clock to Output 453
- 20-10 458
- 20-12 460
- 20-13 461
- 20-14 462
- 21 IIS-BUS INTERFACE 463
- FUNCTIONAL DESCRIPTIONS 464
- 21-3 465
- 21-4 466
- 22 SPI 471
- Pin Control Logic 0 472
- APB I/F 0 472
- Pin Control Logic 1 472
- APB I/F 1 472
- SPI OPERATION 473
- SPI TRANSFER FORMAT 474
- 22-5 475
- SPI SPECIAL REGISTERS 476
- 22-7 477
- 22-8 478
- 23 CAMERA INTERFACE 479
- Figure 23-1 CAMIF Overview 480
- 23-3 481
- CAMERA INTERFACE OPERATION 483
- 23-7 485
- 23-9 487
- 23-11 489
- 23-13 491
- TG 493
- TG 493
- X_WNG 493
- 23-17 495
- 23-19 497
- 23-21 499
- 23-23 501
- 24 AC97 CONTROLLER 503
- AC97 CONTROLLER OPERATION 504
- OPERATION FLOW CHART 506
- SDATA_OUT 507
- SDATA_IN 507
- AC97 POWERDOWN 508
- (NOTE) 511
- 24-11 513
- 24-12 514
- 25 BUS PRIORITIES 515
- 25-2 516
- 26 MECHANICAL DATA 517
- 27 ELECTRICAL DATA 519
- 27-7 525
- 27-9 527
- 27-10 528
- 27-11 529
- 27-12 530
- 27-13 531
- 27-14 532
- 27-15 533
- 27-16 534
- 27-17 535
- 27-18 536
- 27-20 538
- 27-22 540
- 27-23 541
- 27-24 542
- 27-27 545
- 27-28 546
- 27-29 547
- 27-30 548
- 27-31 549
- 27-32 550
- 27-33 551
- 27-36 554
- 27-38 556
- 27-39 557
- NOTES: 557
- 1. HSYNC period 557
- 2. VCLK period 557
- 27-41 559
- 27-42 560
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