Samsung 8-Bit User Manual

21-S3-C9228/P9228-112002USER'S MANUALS3C9228/P92288-Bit CMOSMicrocontrollerRevision 1

S3C9228/P9228 MICROCONTROLLERS ixTable of Contents (Concluded)Chapter 16 Electrical DataOverview...

SAM88RI INSTRUCTION SET S3C9228/P92286-4FLAGS REGISTER (FLAGS)The FLAGS register contains eight bits that describe the current status of CPU operation

S3C9228/P9228 SAM88RCRI INSTRUCTION SET6-5INSTRUCTION SET NOTATIONTable 6-2. Flag Notation ConventionsFlag DescriptionC Carry flagZ Zero flagS Sign fl

SAM88RI INSTRUCTION SET S3C9228/P92286-6Table 6-4. Instruction Notation ConventionsNotation Description Actual Operand Rangecc Condition code See list

S3C9228/P9228 SAM88RCRI INSTRUCTION SET6-7Table 6-5. Opcode Quick ReferenceOPCODE MAPLOWER NIBBLE (HEX)– 0 1 2 3 4 5 6 7U0 DECR1DECIR1ADDr1,r2ADDr1,Ir

SAM88RI INSTRUCTION SET S3C9228/P92286-8Table 6-5. Opcode Quick Reference (Continued)OPCODE MAPLOWER NIBBLE (HEX)– 8 9 A B C D E FU0 LDr1,R2LDr2,R1JRc

S3C9228/P9228 SAM88RCRI INSTRUCTION SET6-9CONDITION CODESThe opcode of a conditional jump always contains a 4-bit field called the condition code (cc)

SAM88RI INSTRUCTION SET S3C9228/P92286-10INSTRUCTION DESCRIPTIONSThis section contains detailed information and programming examples for each instruct

S3C9228/P9228 SAM88RCRI INSTRUCTION SET6-11ADC — Add With CarryADC dst,srcOperation: dst ¨ dst + src + cThe source operand, along with the sett

SAM88RI INSTRUCTION SET S3C9228/P92286-12ADD — AddADD dst,srcOperation: dst ¨ dst + srcThe source operand is added to the destination operand and

S3C9228/P9228 SAM88RCRI INSTRUCTION SET6-13AND — Logical ANDAND dst,srcOperation: dst ¨ dst AND srcThe source operand is logically ANDed with the

SAM88RI INSTRUCTION SET S3C9228/P92286-14CALL — Call ProcedureCALL dstOperation: SP ¨ SP – 1@SP ¨ PCLSP ¨ SP –1@SP ¨ PCHPC ¨ dstThe current contents

S3C9228/P9228 SAM88RCRI INSTRUCTION SET6-15CCF — Complement Carry FlagCCFOperation: C ¨ NOT CThe carry flag (C) is complemented. If C = "1&

SAM88RI INSTRUCTION SET S3C9228/P92286-16CLR — ClearCLR dstOperation: dst ¨ "0"The destination location is cleared to "0".Flags

S3C9228/P9228 SAM88RCRI INSTRUCTION SET6-17COM — ComplementCOM dstOperation: dst ¨ NOT dstThe contents of the destination location are complemente

SAM88RI INSTRUCTION SET S3C9228/P92286-18CP — CompareCP dst,srcOperation: dst – srcThe source operand is compared to (subtracted from) the destinatio

S3C9228/P9228 SAM88RCRI INSTRUCTION SET6-19DEC — DecrementDEC dstOperation: dst ¨ dst – 1The contents of the destination operand are decremented by

SAM88RI INSTRUCTION SET S3C9228/P92286-20DI — Disable InterruptsDIOperation: SYM (2) ¨ 0Bit zero of the system mode register, SYM.2, is cleared to

S3C9228/P9228 SAM88RCRI INSTRUCTION SET6-21EI — Enable InterruptsEIOperation: SYM (2) ¨ 1An EI instruction sets bit 2 of the system mode register,

SAM88RI INSTRUCTION SET S3C9228/P92286-22IDLE — Idle OperationIDLEOperation:The IDLE instruction stops the CPU clock while allowing system clock osci

S3C9228/P9228 SAM88RCRI INSTRUCTION SET6-23INC — IncrementINC dstOperation: dst ¨ dst + 1The contents of the destination operand are incremented

S3C9228/P9228 MICROCONTROLLERS xiList of FiguresFigure Title PageNumber Number1-1 Block Diagram...

SAM88RI INSTRUCTION SET S3C9228/P92286-24IRET — Interrupt ReturnIRET IRETOperation: FLAGS ¨ @SPSP ¨ SP + 1PC ¨ @SPSP ¨ SP + 2SYM(2) ¨ 1

S3C9228/P9228 SAM88RCRI INSTRUCTION SET6-25JP — JumpJP cc,dst (Conditional)JP dst (Unconditional)Operation: If cc is true, PC ¨ dstThe condition

SAM88RI INSTRUCTION SET S3C9228/P92286-26JR — Jump RelativeJR cc,dstOperation: If cc is true, PC ¨ PC + dstIf the condition specified by the c

S3C9228/P9228 SAM88RCRI INSTRUCTION SET6-27LD — LoadLD dst,srcOperation: dst ¨ srcThe contents of the source are loaded into the destination. The s

SAM88RI INSTRUCTION SET S3C9228/P92286-28LD — LoadLD (Continued)Examples: Given: R0 = 01H, R1 = 0AH, register 00H = 01H, register 01H = 20H,register

S3C9228/P9228 SAM88RCRI INSTRUCTION SET6-29LDC/LDE — Load MemoryLDC/LDE dst,srcOperation: dst ¨ srcThis instruction loads a byte from program or da

SAM88RI INSTRUCTION SET S3C9228/P92286-30LDC/LDE — Load MemoryLDC/LDE (Continued)Examples: Given: R0 = 11H, R1 = 34H, R2 = 01H, R3 = 04H, R4 = 00H, R

S3C9228/P9228 SAM88RCRI INSTRUCTION SET6-31LDCD/LDED — Load Memory and DecrementLDCD/LDED dst,srcOperation: dst ¨ srcrr ¨ rr – 1These instruction

SAM88RI INSTRUCTION SET S3C9228/P92286-32LDCI/LDEI — Load Memory and IncrementLDCI/LDEI dst,srcOperation: dst ¨ srcrr ¨ rr + 1These instruction

S3C9228/P9228 SAM88RCRI INSTRUCTION SET6-33NOP — No OperationNOPOperation: No action is performed when the CPU executes this instruction. Typically,

xii S3C9228/P9228 MICROCONTROLLERSList of Figures (Continued)Figure Title PageNumber Number5-1 S3C9-Series Interrupt Type ...

SAM88RI INSTRUCTION SET S3C9228/P92286-34OR — Logical OROR dst,srcOperation: dst ¨ dst OR srcThe source operand is logically ORed with the destin

S3C9228/P9228 SAM88RCRI INSTRUCTION SET6-35POP — Pop From StackPOP dstOperation: dst ¨ @SPSP ¨ SP + 1The contents of the location addressed by

SAM88RI INSTRUCTION SET S3C9228/P92286-36PUSH — Push To StackPUSH srcOperation: SP ¨ SP – 1@SP ¨ srcA PUSH instruction decrements the stack poi

S3C9228/P9228 SAM88RCRI INSTRUCTION SET6-37RCF — Reset Carry FlagRCF RCFOperation: C ¨ 0The carry flag is cleared to logic zero, regardless of its

SAM88RI INSTRUCTION SET S3C9228/P92286-38RET — ReturnRETOperation: PC ¨ @SPSP ¨ SP + 2The RET instruction is normally used to return to the pre

S3C9228/P9228 SAM88RCRI INSTRUCTION SET6-39RL — Rotate LeftRL dstOperation: C ¨ dst (7)dst (0) ¨ dst (7)dst (n + 1) ¨ dst (n), n = 0–6The co

SAM88RI INSTRUCTION SET S3C9228/P92286-40RLC — Rotate Left Through CarryRLC dstOperation: dst (0) ¨ CC ¨ dst (7)dst (n + 1) ¨ dst (n), n = 0–

S3C9228/P9228 SAM88RCRI INSTRUCTION SET6-41RR — Rotate RightRR dstOperation: C ¨ dst (0)dst (7) ¨ dst (0)dst (n) ¨ dst (n + 1), n = 0–6The c

SAM88RI INSTRUCTION SET S3C9228/P92286-42RRC — Rotate Right Through CarryRRC dstOperation: dst (7) ¨ CC ¨ dst (0)dst (n) ¨ dst (n + 1), n = 0

S3C9228/P9228 SAM88RCRI INSTRUCTION SET6-43SBC — Subtract With CarrySBC dst,srcOperation: dst ¨ dst – src – cThe source operand, along with the

S3C9228/P9228 MICROCONTROLLERS xiiiList of Figures (Continued)Figure Title PageNumber Number10-1 Basic Timer Control Register (BTCON) ...

SAM88RI INSTRUCTION SET S3C9228/P92286-44SCF — Set Carry FlagSCFOperation: C ¨ 1The carry flag (C) is set to logic one, regardless of its previous

S3C9228/P9228 SAM88RCRI INSTRUCTION SET6-45SRA — Shift Right ArithmeticSRA dstOperation: dst (7) ¨ dst (7)C ¨ dst (0)dst (n) ¨ dst (n + 1), n

SAM88RI INSTRUCTION SET S3C9228/P92286-46STOP — Stop OperationSTOPOperation:The STOP instruction stops both the CPU clock and system clock and causes

S3C9228/P9228 SAM88RCRI INSTRUCTION SET6-47SUB — SubtractSUB dst,srcOperation: dst ¨ dst – srcThe source operand is subtracted from the destinatio

SAM88RI INSTRUCTION SET S3C9228/P92286-48TCM — Test Complement Under MaskTCM dst,srcOperation: (NOT dst) AND srcThis instruction tests selected bit

S3C9228/P9228 SAM88RCRI INSTRUCTION SET6-49TM — Test Under MaskTM dst,srcOperation: dst AND srcThis instruction tests selected bits in the destinat

SAM88RI INSTRUCTION SET S3C9228/P92286-50XOR — Logical Exclusive ORXOR dst,srcOperation: dst ¨ dst XOR srcThe source operand is logically exclusiv

S3C9228/P9228 CLOCK CIRCUITS7-17 CLOCK CIRCUITSOVERVIEWThe S3C9228 microcontroller has two oscillator circuits: a main clock, and a sub clock circuit.

CLOCK CIRCUITS S3C9228/P92287-2MAIN OSCILLATOR CIRCUITSXINXOUTFigure 7-1. Crystal/Ceramic OscillatorXINXOUTFigure 7-2. External OscillatorXINXOUTRFigu

S3C9228/P9228 CLOCK CIRCUITS7-3CLOCK STATUS DURING POWER-DOWN MODESThe two power-down modes, Stop mode and Idle mode, affect the system clock as follo

xiv S3C9228/P9228 MICROCONTROLLERSList of Figures (Concluded)Figure Title PageNumber Number16-1 Stop Mode Release Timing When Initiated by an External

CLOCK CIRCUITS S3C9228/P92287-4SYSTEM CLOCK CONTROL REGISTER (CLKCON)The system clock control register, CLKCON, is located in address D4H. It is read/

S3C9228/P9228 CLOCK CIRCUITS7-5OSCILLATOR CONTROL REGISTER (OSCCON)The oscillator control register, OSCCON, is located in address D3H. It is read/writ

CLOCK CIRCUITS S3C9228/P92287-6SWITCHING THE CPU CLOCKData loadings in the oscillator control register, OSCCON, determine whether a main or a sub cloc

S3C9228/P9228 CLOCK CIRCUITS7-7STOP CONTROL REGISTER (STPCON)The STOP control register, STPCON, is located in address E0H. It is read/write addressabl

CLOCK CIRCUITS S3C9228/P92287-8NOTES

S3C9228/P9228 RESETRESET and POWER-DOWN8-18 RESETRESET and POWER-DOWNSYSTEM RESETOVERVIEWDuring a power-on reset, the voltage at VDD goes to High leve

RESETRESET and POWER-DOWN S3C9228/P92288-2POWER-DOWN MODESSTOP MODEStop mode is invoked by the instruction STOP. In Stop mode, the operation of the CP

S3C9228/P9228 RESETRESET and POWER-DOWN8-3Using an Internal Interrupt to Release Stop ModeAn internal interrupt, watch timer, can be used to release s

RESETRESET and POWER-DOWN S3C9228/P92288-4HARDWARE RESET RESET VALUESTable 8-1 list the values for CPU and system registers, peripheral control regist

S3C9228/P9228 RESETRESET and POWER-DOWN8-5Table 8-1. Register Values after RESET RESET (Continued)Register Name Mnemonic AddressBit Values after RESET

S3C9228/P9228 MICROCONTROLLERS xvList of TablesTable Title PageNumber Number1-1 Pin Descriptions ...

RESETRESET and POWER-DOWN S3C9228/P92288-6NOTES

S3C9228/P9228 I/O PORTS9-19 I/O PORTSOVERVIEWThe S3C9228/P9228 microcontroller has seven bit-programmable I/O ports, P0-P6. Port 0 is 6-bit port, port

I/O PORTS S3C9228/P92289-2PORT DATA REGISTERSTable 9-2 gives you an overview of the register locations of all seven S3C9228 I/O port data registers. D

S3C9228/P9228 I/O PORTS9-3PORT 0Port 0 is an 6-bit I/O port with individually configurable pins. Port 0 pins are accessed directly by writing orreadin

I/O PORTS S3C9228/P92289-4Port 0 Control Register (P0CON)EBH, Page 0, R/W.7 .6 .5 .4 .3 .2 .1 .0MSB LSBP0.3/BUZ(INT)P0CON bit-pair pin configuration s

S3C9228/P9228 I/O PORTS9-5Port 0 Interrupt Pending Bits (INTPND1.3-.0)D6H, Page 0, R/W.7 .6 .5 .4 .3 .2 .1 .0MSB LSBINTPND1 bit configuration settings

I/O PORTS S3C9228/P92289-6PORT 1Port 1 is an 4-bit I/O port with individually configurable pins. Port 1 pins are accessed directly by writing orreadin

S3C9228/P9228 I/O PORTS9-7Port 1 Interrupt Control Register (P1INT)F1H, Page 0, R/W.7 .6 .5 .4 .3 .2 .1 .0MSB LSBNot usedP1INT bit configuration setti

I/O PORTS S3C9228/P92289-8Port 1 Interrupt Edge Selection Register (P1EDGE)F2H, Page 0, R/W.7 .6 .5 .4 .3 .2 .1 .0MSB LSBP1EDGE bit configuration sett

S3C9228/P9228 I/O PORTS9-9PORT 2Port 2 is an 4-bit I/O port with individually configurable pins. Port 2 pins are accessed directly by writing orreadin

I/O PORTS S3C9228/P92289-10Port 2 Pull-up Control Register (P2PUR)F4H, Page 0, R/W.7 .6 .5 .4 .3 .2 .1 .0MSB LSBP2PUR bit configuration settings:01Ena

S3C9228/P9228 I/O PORTS9-11PORT 3Port 3 is an 2-bit I/O port with individually configurable pins. Port 3 pins are accessed directly by writing orreadi

I/O PORTS S3C9228/P92289-12Port 3 Interrupt Control Register (P3INT)F7H, Page 0, R/W.7 .6 .5 .4 .3 .2 .1 .0MSB LSBNot usedP3INT bit configuration sett

S3C9228/P9228 I/O PORTS9-13Port 3 Interrupt Edge Selection Register (P3EDGE)F8H, Page 0, R/W.7 .6 .5 .4 .3 .2 .1 .0MSB LSBP3EDGE bit configuration set

I/O PORTS S3C9228/P92289-14PORT 4Port 4 is an 8-bit I/O port with individually configurable pins. Port 4 pins are accessed directly by writing orreadi

S3C9228/P9228 I/O PORTS9-15PORT 5Port 5 is an 8-bit I/O port with individually configurable pins. Port 5 pins are accessed directly by writing orreadi

I/O PORTS S3C9228/P92289-16PORT 6Port 6 is an 4-bit I/O port with individually configurable pins. Port 6 pins are accessed directly by writing orreadi

S3C9228/P9228 (Preliminary Spec) BASIC TIMER10-110 BASIC TIMEROVERVIEWBasic timer (BT) can be used in two different ways:— As a watchdog timer to prov

BASIC TIMER S3C9228/P9228 (Preliminary Spec)10-2BASIC TIMER CONTROL REGISTER (BTCON)The basic timer control register, BTCON, is used to select the inp

S3C9228/P9228 (Preliminary Spec) BASIC TIMER10-3BASIC TIMER FUNCTION DESCRIPTIONWatchdog Timer FunctionYou can program the basic timer overflow signal

S3C9228/P9228 MICROCONTROLLERS xviiList of Programming TipsDescription PageNumberChapter 2: Address SpacesAddressing the Common Working Register Area

BASIC TIMER S3C9228/P9228 (Preliminary Spec)10-4NOTE: During a power-on reset operation, the CPU is idle during the required oscillationstabilization

S3C9228/P9228 TIMER 111-111 TIMER 1ONE 16-BIT TIMER MODE (TIMER 1)The 16-bit timer 1 is used in one 16-bit timer or two 8-bit timers mode. If TACON.7

TIMER 1 S3C9228/P922811-2Timer 1 Control Register (TACON)You use the timer 1 control register, TACON, to— Enable the timer 1 operating (interval timer

S3C9228/P9228 TIMER 111-3NOTE: When one 16-bit timer mode (TACON.7 <- "1": Timer 1)TACON.6-.4MUX1/81/641/2561/512INTPND2.0TAOUTT1INT1/1DI

TIMER 1 S3C9228/P922811-4TWO 8-BIT TIMERS MODE (TIMER A and B)OVERVIEWThe 8-bit timer A and B are the 8-bit general-purpose timers. Timer A and B have

S3C9228/P9228 TIMER 111-5TACON and TBCON are located in page 0, at address BBH and BAH, and is read/write addressable usingregister addressing mode.A

TIMER 1 S3C9228/P922811-6Timer B Control Register (TBCON)BAH, R/W.7 .6 .5 .4 .3 .2 .1 .0MSB LSBTimer B match interrupt enable bit:0 = Disable match i

S3C9228/P9228 TIMER 111-7FUNCTION DESCRIPTIONInterval Timer Function (Timer A and Timer B)The timer A and B module can generate an interrupt: the time

TIMER 1 S3C9228/P922811-8NOTE: When two 8-bit timers mode (TACON.7 <- "0": Timer A)TACON.6-.4MUX1/81/641/2561/512INTPND2.0TAOUTTAINTDIVRf

S3C9228/P9228 TIMER 111-91/11/81/641/2561/512NOTE: When two 8-bit timers mode (TACON.7 <- "0": Timer B)TBCON.6-.4MUXINTPND2.1TBINTDIVRfxt

TIMER 1 S3C9228/P922811-10NOTES

S3C9228/P9228 WATCH TIMER12-112 WATCH TIMEROVERVIEWWatch timer functions include real-time and watch-time measurement and interval timing for the syst

WATCH TIMER S3C9228/P922812-2WATCH TIMER CONTROL REGISTER (WTCON)The watch timer control register, WTCON is used to select the input clock source, th

S3C9228/P9228 WATCH TIMER12-3WATCH TIMER CIRCUIT DIAGRAMWT INT EnableWTCON.1WTCON.2WTCON.3WTCON.4WTCON.5WTCON.6Enable/DisableSelectorCircuitMUXINTPND2

WATCH TIMER S3C9228/P922812-4NOTES

S3C9228/P9228 LCD CONTROLLER/DRIVER13-113 LCD CONTROLLER/DRIVEROVERVIEWThe S3C9228/P9228 microcontroller can directly drive an up-to-128-dot (16segmen

LCD CONTROLLER/DRIVER S3C9228/P922813-2LCD CIRCUIT DIAGRAMSEG15/P5.3COM4/SEG19/P5.7COM7/SEG16/P5.416016Data BUSPortLatchLPOTDisplayRAM(Page1)PortLatch

S3C9228/P9228 LCD CONTROLLER/DRIVER13-3LCD RAM ADDRESS AREARAM addresses of page 1 are used as LCD data memory. When the bit value of a display segmen

LCD CONTROLLER/DRIVER S3C9228/P922813-4LCD MODE CONTROL REGISTER (LMOD)A LMOD is located in page 0, at address FEH, and is read/write addressable usin

S3C9228/P9228 LCD CONTROLLER/DRIVER13-5LCD PORT CONTROL REGISTERThe LCD port control register LPOT is used to control LCD signal pins or normal I/O pi

S3C9228/P92288-BIT CMOSMICROCONTROLLERSUSER'S MANUALRevision 1

S3C9228/P9228 MICROCONTROLLERS xixList of Register DescriptionsRegister Full Register Name PageIdentifier NumberADCON A/D Converter Control Register..

LCD CONTROLLER/DRIVER S3C9228/P922813-6LCD VOLTAGE DIVIDING RESISTORS1/5 BiasS3C9228/P9228VDDRRRRRLMOD.4VLC1VLC2VLC3VLC4VLC5VSS1/4 BiasS3C9228/P9228VD

S3C9228/P9228 LCD CONTROLLER/DRIVER13-71 FrameFRVDDVSSCOM0COM1COM2COM3COM4COM5COM6COM7COM1 VLC2 (VLC3)VLC4VSSVDDVLC1SEG0 VLC2 (VLC3)VLC4VSSVDDVLC1COM2

LCD CONTROLLER/DRIVER S3C9228/P922813-81 FrameVDDVSS0 1 230 1 23COM1VSSVDDVLC1(VLC2)VLC3(VLC4)COM2VSSVDDVLC1(VLC2)VLC3(VLC4)COM3VSSVDDVLC1(VLC2)VLC3(V

S3C9228/P9228 LCD CONTROLLER/DRIVER13-91 FrameVDDVSS012COM1VSSVDDVLC1(VLC2)VLC3(VLC4)COM2VSSVDDVLC1(VLC2)VLC3(VLC4)SEG0VSSVDDVLC1(VLC2)VLC3(VLC4)SEG1V

LCD CONTROLLER/DRIVER S3C9228/P922813-10NOTES

S3C9228/P9228 A/D CONVERTER14-114 10-BIT ANALOG-TO-DIGITAL CONVERTEROVERVIEWThe 10-bit A/D converter (ADC) module uses successive approximation logic

A/D CONVERTER S3C9228/P922814-2CONVERSION TIMINGThe A/D conversion process requires 4 steps (4 clock edges) to convert each bit and 10 clocks to set-

S3C9228/P9228 A/D CONVERTER14-3Conversion Data Register ADDATAH/ADDATALD1H/D2H, Page 0, Read Only.9 .8 .7 .6 .5 .4 .3 .2MSB LSB (ADDATAH)- - - - - - .

A/D CONVERTER S3C9228/P922814-4S3C9228AD0-AD3AnalogInput PinVDD101C(VSS ≤ ADC input ≤ VDD)Figure 14-4. Recommended A/D Converter Circuit for Highest

S3C9228/P9228 SERIAL I/O INTERFACE15-115 SERIAL I/O INTERFACEOVERVIEWSerial I/O modules, SIO can interface with various types of external device that

SERIAL I/O INTERFACE S3C9228/P922815-2SIO CONTROL REGISTERS (SIOCON)The control register for serial I/O interface module, SIOCON, is located at E1H in

S3C9228/P9228 SERIAL I/O INTERFACE15-3SIO PRE-SCALER REGISTER (SIOPS)The prescaler register for serial I/O interface module, SIOPS, are located at E3H

SERIAL I/O INTERFACE S3C9228/P922815-4SERIAL I/O TIMING DIAGRAM (SIO)SOTransmitCompleteSIO INTSet SIOCON.3DO7 DO6 DO5 DO4 DO3 DO2 DO1 DO0DI7 DI6 DI5 D

S3C9228/P9228 ELECTRICAL DATA16-116 ELECTRICAL DATAOVERVIEWIn this chapter, S3C9228/P9228 electrical characteristics are presented in tables and graph

ELECTRICAL DATA S3C9228/P922816-2Table 16-1. Absolute Maximum Ratings(TA = 25°C)Parameter Symbol Conditions Rating UnitSupply voltageVDD– – 0.3 to +

S3C9228/P9228 ELECTRICAL DATA16-3Table 16-2. D.C. Electrical Characteristics (Continued)(TA = – 25°C to + 85°C, VDD = 2.0 V to 5.5 V)Parameter

ELECTRICAL DATA S3C9228/P922816-4Table 16-2. D.C. Electrical Characteristics (Concluded)(TA = – 25°C to + 85°C, VDD = 2.0 V to 5.5 V)Parameter

S3C9228/P9228 ELECTRICAL DATA16-5Table 16-3. Data Retention Supply Voltage in Stop Mode(TA = – 25 °C to + 85 °C)Parameter Symbol Conditions Min Ty

ELECTRICAL DATA S3C9228/P922816-6Execution ofSTOP InstrctionRESETOccurs~~VDDDR~~Stop ModeOscillationStabilizationTImeNormalOperating ModeData Retentio

S3C9228/P9228 ELECTRICAL DATA16-7Table 16-5. A.C. Electrical Characteristics(TA = – 25°C to + 85°C, VDD = 2.0 V to 5.5 V)Parameter Symbol Condit

S3C9228/P9228 MICROCONTROLLERS xxiList of Instruction DescriptionsInstruction Full Instruction Name PageMnemonic NumberADC Add With Carry ...

ELECTRICAL DATA S3C9228/P922816-8Table 16-6. A/D Converter Electrical Characteristics(TA = – 25°C to + 85°C, VDD = 2.7 V to 5.5 V, VSS = 0 V)Par

S3C9228/P9228 ELECTRICAL DATA16-9RESETtRSL0.2 VDDFigure 16-4. Input Timing for RESETRESETtKHtKL0.2VDDSCKtKCY0.8VDD0.8VDD0.2VDDtSIKtKSISISOtKSOOutput D

ELECTRICAL DATA S3C9228/P922816-10Table 16-7. Main Oscillation Characteristics (TA = – 25°C to + 85°C)Oscillator Clock Configuration Parameter Te

S3C9228/P9228 ELECTRICAL DATA16-11Table 16-9. Main Oscillation Stabilization Time(TA = – 25 °C to + 85 °C, VDD = 2.0 V to 5.5 V)Oscillator Test

ELECTRICAL DATA S3C9228/P922816-12Table 16-10. Sub Oscillation Stabilization Time(TA = – 25 °C to + 85 °C, VDD = 2.0 V to 5.5 V)Oscillator Test

S3C9228/P9228 ELECTRICAL DATA16-13 2 MHz6.25 kHz (main)/8.2 kHz(sub)1 2 6Supply Voltage (V)Instruction Clock = 1/4n x oscillator frequency (n = 1, 2,

ELECTRICAL DATA S3C9228/P922816-14NOTES

S3C9228/P9228 MECHANICAL DATA17-117 MECHANICAL DATAOVERVIEWThe S3C9228/P9228 microcontroller is currently available in a 42-pin SDIP and 44-pin QFP pa

MECHANICAL DATA S3C9228/P922817-244-QFP-1010B#44NOTE: Dimensions are in millimeters.10.00 ± 0.213.20 ± 0.310.00 ± 0.213.20 ± 0.3#10.35+ 0.10- 0.050.

S3C9228/P9228 S3P9228 OTP 18-118 S3P9228 OTPOVERVIEWThe S3P9228 single-chip CMOS microcontroller is the OTP (One Time Programmable) version of the S3

S3C9228/P9228 PRODUCT OVERVIEW1-11 PRODUCT OVERVIEWSAM88RCRI PRODUCT FAMILYSamsung's SAM88RCRI family of 8-bit single-chip CMOS microcontrollers

S3P9228 OTP S3C9228/P922818-2 COM1/P6.2COM0/P6.3P0.0/TAOUT/INTP0.1/T1CLK/INTP0.2/INTP0.3/BUZ/INTP1.0/AD0/INTP1.1/AD1/INTSDAT/P1.2/AD2/INTSCLK/P1.3/AD

S3C9228/P9228 S3P9228 OTP 18-3Table 18-1. Descriptions of Pins Used to Read/Write the EPROMMain Chip During ProgrammingPin Name Pin Name Pin No. I/O

S3P9228 OTP S3C9228/P922818-4 Table 18-4. D.C. Electrical Characteristics(TA = – 25°C to + 85°C, VDD = 2.0 V to 5.5 V)Parameter Symbol Condit

S3C9228/P9228 S3P9228 OTP 18-52 MHz6.25 kHz (main)/8.2 kHz(sub)1 2 6Supply Voltage (V)Instruction Clock = 1/4n x oscillator frequency (n = 1, 2, 8, 1

S3P9228 OTP S3C9228/P922818-6 NOTES

S3C9228/P9228 DEVELOPMENT TOOLS19-119 DEVELOPMENT TOOLSOVERVIEWSamsung provides a powerful and easy-to-use development support system in turn key form

DEVELOPMENT TOOLS S3C9228/P922819-2BUSSMDS2+RS-232CPODProbeAdapterPROM/OTP Writer UnitRAM Break/Display UnitTrace/Timer UnitSAM8 Base UnitPower Suppl

S3C9228/P9228 DEVELOPMENT TOOLS19-3TB9228 TARGET BOARDThe TB9228 target board is used for the S3C9228 microcontroller. It is supported by the SMDS2+ d

DEVELOPMENT TOOLS S3C9228/P922819-4Table 19-1. Power Selection Settings for TB9228"To User_VCC"SettingsOperating Mode CommentsTo User_VCCOf

S3C9228/P9228 DEVELOPMENT TOOLS19-5SMDS2+ Selection (SAM8)In order to write data into program memory that is available in SMDS2+, the target board sho

PRODUCT OVERVIEW S3C9228/P92281-2FEATURESCPU• SAM88RCRI CPU coreMemory• 8192 × 8 bits program memory (ROM)• 264 × 8 bits data memory (RAM)(Including L

DEVELOPMENT TOOLS S3C9228/P922819-6J10142-SDIPJ10244-QFP1234567891011121314151617181920214344454642414039383736353433323130292827262524232250494847P6

S3C9228/P9228 DEVELOPMENT TOOLS19-7 Target Board Target SystemTarget Cable for ConnectorPart Name: AP42SDOrder Code: SM6538J1011 4221 22J1011 4221 225

DEVELOPMENT TOOLS S3C9228/P922819-8NOTES

S3C9228/P9228 PRODUCT OVERVIEW1-11 PRODUCT OVERVIEWSAM88RCRI PRODUCT FAMILYSamsung's SAM88RCRI family of 8-bit single-chip CMOS microcontrollers

PRODUCT OVERVIEW S3C9228/P92281-2FEATURESCPU• SAM88RCRI CPU coreMemory• 8192 × 8 bits program memory (ROM)• 264 × 8 bits data memory (RAM)(Including L

S3C9228/P9228 PRODUCT OVERVIEW1-3BLOCK DIAGRAM8-Bit Timer/CounterAPort I/O and InterruptControlSAM88RCRI CPURESETXINXTINI/O Port 08-KbyteROM264-ByteRe

PRODUCT OVERVIEW S3C9228/P92281-4PIN ASSIGNMENTS12345678910111213141516171819202122S3C9228(44-QFP)P1.0/AD0/INTP1.1/AD1/INTP1.2/AD2/INTP1.3/AD3/INTVDDV

S3C9228/P9228 PRODUCT OVERVIEW1-5COM1/P6.2COM0/P6.3P0.0/TAOUT/INTP0.1/T1CLK/INTP0.2/INTP0.3/BUZ/INTP1.0/AD0/INTP1.1/AD1/INTP1.2/AD2/INTP1.3/AD3/INTVDD

PRODUCT OVERVIEW S3C9228/P92281-6PIN DESCRIPTIONSTable 1-1. Pin DescriptionsPin Names PinTypePin Description CircuitNumberPinNumbersSharePinsP0.0P0.1P

S3C9228/P9228 PRODUCT OVERVIEW1-7 Table 1-1. Pin Descriptions (Continued)Pin Names PinTypePin Description CircuitNumberPinNumbersSharePinsVDD, VSS– Po

S3C9228/P9228 PRODUCT OVERVIEW1-3BLOCK DIAGRAM8-Bit Timer/CounterAPort I/O and InterruptControlSAM88RCRI CPURESETXINXTINI/O Port 08-KbyteROM264-ByteRe

PRODUCT OVERVIEW S3C9228/P92281-8PIN CIRCUIT DIAGRAMSRESETVDDPull-UpResistorNoise FilterFigure 1-4. Pin Circuit Type BVDDOutputOutputDisableDataVSSFig

S3C9228/P9228 PRODUCT OVERVIEW1-9VDDPull-upEnableVDDI/OPull-upResistorOutputDisableDataExternalInterruptInputOpen-DrainFigure 1-7. Pin Circuit Type E-

PRODUCT OVERVIEW S3C9228/P92281-10OutSEG/COMVLC3OutputDisableVLC2VLC1VSSVLC4VLC5Figure 1-9. Pin Circuit Type H-23

S3C9228/P9228 PRODUCT OVERVIEW1-11VDDPull-upEnableVDDI/OPull-upResistorDataOpen-Drain ENCircuitType H-23LCD Out ENCOM/SEGOutputDisableFigure 1-10. Pin

PRODUCT OVERVIEW S3C9228/P92281-12VDDPull-upEnableVDDI/OPull-upResistorDataOpen-Drain ENCircuitType H-23LCD Out ENCOM/SEGOutputDisablePortEnable(LMOD.

S3C9228/P9228 ADDRESS SPACES2-12 ADDRESS SPACESOVERVIEWThe S3C9228/P9228 microcontroller has three kinds of address space:— Program memory (ROM)— Inte

ADDRESS SPACES S3C9228/P92282-2PROGRAM MEMORY (ROM)Program memory (ROM) stores program code or table data. The S3C9228 has 8K bytes of mask-programabl

S3C9228/P9228 ADDRESS SPACES2-3REGISTER ARCHITECTUREThe upper 72 bytes of the S3C9228/P9228's internal register file are addressed as working reg

ADDRESS SPACES S3C9228/P92282-4COMMON WORKING REGISTER AREA (C0H–CFH)The SAM88RCRI register architecture provides an efficient method of working regis

S3C9228/P9228 ADDRESS SPACES2-5SYSTEM STACKS3C9-series microcontrollers use the system stack for subroutine calls and returns and to store data. The P

PRODUCT OVERVIEW S3C9228/P92281-4PIN ASSIGNMENTS12345678910111213141516171819202122S3C9228(44-QFP)P1.0/AD0/INTP1.1/AD1/INTP1.2/AD2/INTP1.3/AD3/INTVDDV

ADDRESS SPACES S3C9228/P92282-6++ PROGRAMMING TIP — Standard Stack Operations Using PUSH and POPThe following example shows you how to perform stack o

S3C9228/P9228 ADDRESSING MODES3-13 ADDRESSING MODESOVERVIEWInstructions that are stored in program memory are fetched for execution using the program

ADDRESSING MODES S3C9228/P92283-2REGISTER ADDRESSING MODE (R)In Register addressing mode, the operand is the content of a specified register (see Figu

S3C9228/P9228 ADDRESSING MODES3-3INDIRECT REGISTER ADDRESSING MODE (IR)In Indirect Register (IR) addressing mode, the content of the specified registe

ADDRESSING MODES S3C9228/P92283-4INDIRECT REGISTER ADDRESSING MODE (Continued)dstOPCODEPAIRPoints toRigister PairExampleInstructionReferencesProgramMe

S3C9228/P9228 ADDRESSING MODES3-5INDIRECT REGISTER ADDRESSING MODE (Continued)dstOPCODEOPERAND4-BitWorkingRegisterAddressPoint to theWoking Register(1

ADDRESSING MODES S3C9228/P92283-6INDIRECT REGISTER ADDRESSING MODE (Concluded)dstOPCODE4-Bit WorkingRegister AddressSample Instructions:LCD R5,@RR6 ;

S3C9228/P9228 ADDRESSING MODES3-7INDEXED ADDRESSING MODE (X)Indexed (X) addressing mode adds an offset value to a base address during instruction exec

ADDRESSING MODES S3C9228/P92283-8INDEXED ADDRESSING MODE (Continued)Point to WorkingRegister Pair(1 of 8)LSB Selects16-Bitaddressadded tooffsetdstOPCO

S3C9228/P9228 ADDRESSING MODES3-9INDEXED ADDRESSING MODE (Concluded)Point to WorkingRegister Pair(1 of 8)LSB Selects16-Bitaddressadded tooffsetProgram

S3C9228/P9228 PRODUCT OVERVIEW1-5COM1/P6.2COM0/P6.3P0.0/TAOUT/INTP0.1/T1CLK/INTP0.2/INTP0.3/BUZ/INTP1.0/AD0/INTP1.1/AD1/INTP1.2/AD2/INTP1.3/AD3/INTVDD

ADDRESSING MODES S3C9228/P92283-10DIRECT ADDRESS MODE (DA)In Direct Address (DA) mode, the instruction provides the operand's 16-bit memory addre

S3C9228/P9228 ADDRESSING MODES3-11DIRECT ADDRESS MODE (Continued)OPCODEProgram MemoryUpper Address ByteProgramMemoryAddressUsedLower Address ByteSampl

ADDRESSING MODES S3C9228/P92283-12RELATIVE ADDRESS MODE (RA)In Relative Address (RA) mode, a two's-complement signed displacement between – 128

S3C9228/P9228 CONTROL REGISTERS4-14 CONTROL REGISTERSOVERVIEWIn this section, detailed descriptions of the S3C9228/P9228 control registers are present

CONTROL REGISTERS S3C9228/P92284-2Table 4-1. System and Peripheral Control Registers (Page 0)Register Name Mnemonic Address (Page 0) R/WDecimal HexPor

S3C9228/P9228 CONTROL REGISTERS4-3Table 4-1. System and Peripheral Control Registers (Page 0)Register Name Mnemonic Address (Page 0) R/WDecimal HexLoc

CONTROL REGISTERS S3C9228/P92284-4FLAGS - System Flags Register.7.6.5Bit IdentifierRESET RESET ValueRead/WriteR = Read-onlyW = Write-onlyR/W = Read/wr

S3C9228/P9228 CONTROL REGISTERS4-5ADCON — A/D Converter Control Register D0HBit Identifier .7 .6 .5 .4 .3 .2 .1 .0RESETRESET Value– – 0 0 0 0 0 0Read/

CONTROL REGISTERS S3C9228/P92284-6BTCON — Basic Timer Control Register DCHBit Identifier .7 .6 .5 .4 .3 .2 .1 .0RESETRESET Value0 0 0 0 0 0 0 0Read/Wr

S3C9228/P9228 CONTROL REGISTERS4-7CLKCON — System Clock Control Register D4HBit Identifier .7 .6 .5 .4 .3 .2 .1 .0RESETRESET Value0 0 0 0 0 0 0 0Re

PRODUCT OVERVIEW S3C9228/P92281-6PIN DESCRIPTIONSTable 1-1. Pin DescriptionsPin Names PinTypePin Description CircuitNumberPinNumbersSharePinsP0.0P0.1P

CONTROL REGISTERS S3C9228/P92284-8FLAGS — System Flags Register D5HBit Identifier .7 .6 .5 .4 .3 .2 .1 .0RESETRESET Valuex x x x – – – –Read/WriteR/W

S3C9228/P9228 CONTROL REGISTERS4-9INTPND1 — Interrupt Pending Register 1 D6HBit Identifier .7 .6 .5 .4 .3 .2 .1 .0RESETRESET Value0 0 0 0 0 0 0 0Read/

CONTROL REGISTERS S3C9228/P92284-10INTPND2 — Interrupt Pending Register 2 D7HBit Identifier .7 .6 .5 .4 .3 .2 .1 .0RESETRESET Value– – 0 0 0 0 0 0Read

S3C9228/P9228 CONTROL REGISTERS4-11LMOD — LCD Mode Control Register FEHBit Identifier .7 .6 .5 .4 .3 .2 .1 .0RESETRESET Value– 0 0 0 0 0 0 0Read/Write

CONTROL REGISTERS S3C9228/P92284-12LPOT — LCD Port Control Register D8HBit Identifier .7 .6 .5 .4 .3 .2 .1 .0RESETRESET Value– 0 0 0 0 0 0 0Read/Write

S3C9228/P9228 CONTROL REGISTERS4-13OSCCON — Oscillator Control Register D3HBit Identifier .7 .6 .5 .4 .3 .2 .1 .0RESETRESET Value– – – – 0 0 – 0Read

CONTROL REGISTERS S3C9228/P92284-14P0CON – Port 0 Control Register EBHBit Identifier .7 .6 .5 .4 .3 .2 .1 .0RESETRESET Value0 0 0 0

S3C9228/P9228 CONTROL REGISTERS4-15P0INT –Port 0 Interrupt Enable Register EDHBit Identifier .7 .6 .5 .4 .3 .2 .1 .0RESETRESET Value– – – – 0 0 0 0R

CONTROL REGISTERS S3C9228/P92284-16P0PUR –Port 0 Pull-up Resistors Enable Register ECHBit Identifier .7 .6 .5 .4 .3 .2 .1 .0RESETRESET Value– – – –

S3C9228/P9228 CONTROL REGISTERS4-17P0EDGE –Port 0 Interrupt Edge Selection Register EEHBit Identifier .7 .6 .5 .4 .3 .2 .1 .0RESETRESET Value– – – –

S3C9228/P9228 PRODUCT OVERVIEW1-7 Table 1-1. Pin Descriptions (Continued)Pin Names PinTypePin Description CircuitNumberPinNumbersSharePinsVDD, VSS– Po

CONTROL REGISTERS S3C9228/P92284-18P1CON – Port 1 Control Register EFHBit Identifier .7 .6 .5 .4 .3 .2 .1 .0RESETRESET Value0 0 0 0

S3C9228/P9228 CONTROL REGISTERS4-19P1INT –Port 1 Interrupt Enable Register F1HBit Identifier .7 .6 .5 .4 .3 .2 .1 .0RESETRESET Value– – – – 0 0 0 0R

CONTROL REGISTERS S3C9228/P92284-20P1PUR –Port 1 Pull-up Resistors Enable Register F0HBit Identifier .7 .6 .5 .4 .3 .2 .1 .0RESETRESET Value– – – –

S3C9228/P9228 CONTROL REGISTERS4-21P1EDGE –Port 1 Interrupt Edge Selection Register F2HBit Identifier .7 .6 .5 .4 .3 .2 .1 .0RESETRESET Value– – – –

CONTROL REGISTERS S3C9228/P92284-22P2CON – Port 2 Control Register F3HBit Identifier .7 .6 .5 .4 .3 .2 .1 .0RESETRESET Value0 0 0 0

S3C9228/P9228 CONTROL REGISTERS4-23P2PUR –Port 2 Pull-up Resistors Enable Register F4HBit Identifier .7 .6 .5 .4 .3 .2 .1 .0RESETRESET Value– – – –

CONTROL REGISTERS S3C9228/P92284-24P3CON – Port 3 Control Register F5HBit Identifier .7 .6 .5 .4 .3 .2 .1 .0RESETRESET Value– – – –

S3C9228/P9228 CONTROL REGISTERS4-25P3INT –Port 3 Interrupt Enable Register F7HBit Identifier .7 .6 .5 .4 .3 .2 .1 .0RESETRESET Value– – – – – – 0 0R

CONTROL REGISTERS S3C9228/P92284-26P3PUR –Port 3 Pull-up Resistors Enable Register F6HBit Identifier .7 .6 .5 .4 .3 .2 .1 .0RESETRESET Value– – – –

S3C9228/P9228 CONTROL REGISTERS4-27P3EDGE –Port 3 Interrupt Edge Selection Register F8HBit Identifier .7 .6 .5 .4 .3 .2 .1 .0RESETRESET Value– – – –

Important NoticeThe information in this publication has beencarefully checked and is believed to be entirelyaccurate at the time of publication. Samsu

PRODUCT OVERVIEW S3C9228/P92281-8PIN CIRCUIT DIAGRAMSRESETVDDPull-UpResistorNoise FilterFigure 1-4. Pin Circuit Type BVDDOutputOutputDisableDataVSSFig

CONTROL REGISTERS S3C9228/P92284-28P4CONH – Port 4 Control Register High Byte F9HBit Identifier .7 .6 .5 .4 .3 .2 .1 .0RESETRESET Val

S3C9228/P9228 CONTROL REGISTERS4-29P4CONL–Port 4 Control Register Low Byte FAHBit Identifier .7 .6 .5 .4 .3 .2 .1 .0RESETRESET Value0 0 0 0 0 0 0 0R

CONTROL REGISTERS S3C9228/P92284-30P5CONH – Port 5 Control Register High Byte FBHBit Identifier .7 .6 .5 .4 .3 .2 .1 .0RESETRESET Value0 0 0 0 0 0 0

S3C9228/P9228 CONTROL REGISTERS4-31P5CONL – Port 5 Control Register Low Byte FCHBit Identifier .7 .6 .5 .4 .3 .2 .1 .0RESETRESET Value0 0 0 0 0 0 0

CONTROL REGISTERS S3C9228/P92284-32P6CON – Port 6 Control Register High Byte FDHBit Identifier .7 .6 .5 .4 .3 .2 .1 .0RESETRESET Value0 0 0 0 0 0 0

S3C9228/P9228 CONTROL REGISTERS4-33SIOCON — SIO Control Register E1HBit Identifier .7 .6 .5 .4 .3 .2 .1 .0RESETRESET Value0 0 0 0 0 0 0 –Read/WriteR/W

CONTROL REGISTERS S3C9228/P92284-34STPCON – Stop Control Register E0HBit Identifier .7 .6 .5 .4 .3 .2 .1 .0RESETRESET Value0 0 0 0 0 0 0 0Read/Write

S3C9228/P9228 CONTROL REGISTERS4-35SYM — System Mode Register DFHBit Identifier.7.6 .5 .4 .3 .2 .1 .0RESETRESET Value– – – – 0 0 0 0Read/Write– – – –

CONTROL REGISTERS S3C9228/P92284-36TACON — Timer 1/A Control Register BBHBit Identifier .7 .6 .5 .4 .3 .2 .1 .0RESETRESET Value0 0 0 0 0 0 0 –Read/Wri

S3C9228/P9228 CONTROL REGISTERS4-37TBCON — Timer B Control Register BAHBit Identifier .7 .6 .5 .4 .3 .2 .1 .0RESETRESET Value– 0 0 0 0 0 0 –Read/Write

S3C9228/P9228 PRODUCT OVERVIEW1-9VDDPull-upEnableVDDI/OPull-upResistorOutputDisableDataExternalInterruptInputOpen-DrainFigure 1-7. Pin Circuit Type E-

CONTROL REGISTERS S3C9228/P92284-38WTCON — Watch Timer Control Register DAHBit Identifier .7 .6 .5 .4 .3 .2 .1 .0RESETRESET Value0 0 0 0 0 0 0 –Read/W

S3C9228/P9228 INTERRUPT STRUCTURE5-15 INTERRUPT STRUCTUREOVERVIEWThe SAM88RCRI interrupt structure has two basic components: a vector, and sources. Th

INTERRUPT STRUCTURE S3C9228/P92285-2INTERRUPT PENDING FUNCTION TYPESWhen the interrupt service routine has executed, the application program's se

S3C9228/P9228 INTERRUPT STRUCTURE5-3INTERRUPT SOURCE SERVICE SEQUENCEThe interrupt request polling and servicing sequence is as follows:1. A source ge

INTERRUPT STRUCTURE S3C9228/P92285-4S3C9228/P9228 INTERRUPT STRUCTUREThe S3C9228/P9228 microcontroller has fourteen peripheral interrupt sources:— Tim

S3C9228/P9228 INTERRUPT STRUCTURE5-5SYM.3(EI, DI)P0INT.0P0.0 External InterriptP0INT.1P0.1 External InterriptP0.3 External InterriptP0.2 External Inte

INTERRUPT STRUCTURE S3C9228/P92285-6Programming Tip — How to clear an interrupt pending bitAs the following examples are shown, a load instruction sho

S3C9228/P9228 SAM88RCRI INSTRUCTION SET6-16 SAM88RCRI INSTRUCTION SETOVERVIEWThe SAM88RCRI instruction set is designed to support the large register f

SAM88RI INSTRUCTION SET S3C9228/P92286-2Table 6-1. Instruction Group SummaryMnemonic Operands InstructionLoad InstructionsCLR dst ClearLD dst,src Load

S3C9228/P9228 SAM88RCRI INSTRUCTION SET6-3Table 6-1. Instruction Group Summary (Continued)Mnemonic Operands InstructionProgram Control InstructionsCAL

PRODUCT OVERVIEW S3C9228/P92281-10OutSEG/COMVLC3OutputDisableVLC2VLC1VSSVLC4VLC5Figure 1-9. Pin Circuit Type H-23

SAM88RI INSTRUCTION SET S3C9228/P92286-4FLAGS REGISTER (FLAGS)The FLAGS register contains eight bits that describe the current status of CPU operation

S3C9228/P9228 SAM88RCRI INSTRUCTION SET6-5INSTRUCTION SET NOTATIONTable 6-2. Flag Notation ConventionsFlag DescriptionC Carry flagZ Zero flagS Sign fl

SAM88RI INSTRUCTION SET S3C9228/P92286-6Table 6-4. Instruction Notation ConventionsNotation Description Actual Operand Rangecc Condition code See list

S3C9228/P9228 SAM88RCRI INSTRUCTION SET6-7Table 6-5. Opcode Quick ReferenceOPCODE MAPLOWER NIBBLE (HEX)– 0 1 2 3 4 5 6 7U0 DECR1DECIR1ADDr1,r2ADDr1,Ir

SAM88RI INSTRUCTION SET S3C9228/P92286-8Table 6-5. Opcode Quick Reference (Continued)OPCODE MAPLOWER NIBBLE (HEX)– 8 9 A B C D E FU0 LDr1,R2LDr2,R1JRc

S3C9228/P9228 SAM88RCRI INSTRUCTION SET6-9CONDITION CODESThe opcode of a conditional jump always contains a 4-bit field called the condition code (cc)

SAM88RI INSTRUCTION SET S3C9228/P92286-10INSTRUCTION DESCRIPTIONSThis section contains detailed information and programming examples for each instruct

S3C9228/P9228 SAM88RCRI INSTRUCTION SET6-11ADC — Add With CarryADC dst,srcOperation: dst ¨ dst + src + cThe source operand, along with the sett

SAM88RI INSTRUCTION SET S3C9228/P92286-12ADD — AddADD dst,srcOperation: dst ¨ dst + srcThe source operand is added to the destination operand and

S3C9228/P9228 SAM88RCRI INSTRUCTION SET6-13AND — Logical ANDAND dst,srcOperation: dst ¨ dst AND srcThe source operand is logically ANDed with the

S3C9228/P9228 PRODUCT OVERVIEW1-11VDDPull-upEnableVDDI/OPull-upResistorDataOpen-Drain ENCircuitType H-23LCD Out ENCOM/SEGOutputDisableFigure 1-10. Pin

SAM88RI INSTRUCTION SET S3C9228/P92286-14CALL — Call ProcedureCALL dstOperation: SP ¨ SP – 1@SP ¨ PCLSP ¨ SP –1@SP ¨ PCHPC ¨ dstThe current contents

S3C9228/P9228 SAM88RCRI INSTRUCTION SET6-15CCF — Complement Carry FlagCCFOperation: C ¨ NOT CThe carry flag (C) is complemented. If C = "1&

SAM88RI INSTRUCTION SET S3C9228/P92286-16CLR — ClearCLR dstOperation: dst ¨ "0"The destination location is cleared to "0".Flags

S3C9228/P9228 SAM88RCRI INSTRUCTION SET6-17COM — ComplementCOM dstOperation: dst ¨ NOT dstThe contents of the destination location are complemente

SAM88RI INSTRUCTION SET S3C9228/P92286-18CP — CompareCP dst,srcOperation: dst – srcThe source operand is compared to (subtracted from) the destinatio

S3C9228/P9228 SAM88RCRI INSTRUCTION SET6-19DEC — DecrementDEC dstOperation: dst ¨ dst – 1The contents of the destination operand are decremented by

SAM88RI INSTRUCTION SET S3C9228/P92286-20DI — Disable InterruptsDIOperation: SYM (2) ¨ 0Bit zero of the system mode register, SYM.2, is cleared to

S3C9228/P9228 SAM88RCRI INSTRUCTION SET6-21EI — Enable InterruptsEIOperation: SYM (2) ¨ 1An EI instruction sets bit 2 of the system mode register,

SAM88RI INSTRUCTION SET S3C9228/P92286-22IDLE — Idle OperationIDLEOperation:The IDLE instruction stops the CPU clock while allowing system clock osci

S3C9228/P9228 SAM88RCRI INSTRUCTION SET6-23INC — IncrementINC dstOperation: dst ¨ dst + 1The contents of the destination operand are incremented

PRODUCT OVERVIEW S3C9228/P92281-12VDDPull-upEnableVDDI/OPull-upResistorDataOpen-Drain ENCircuitType H-23LCD Out ENCOM/SEGOutputDisablePortEnable(LMOD.

SAM88RI INSTRUCTION SET S3C9228/P92286-24IRET — Interrupt ReturnIRET IRETOperation: FLAGS ¨ @SPSP ¨ SP + 1PC ¨ @SPSP ¨ SP + 2SYM(2) ¨ 1

S3C9228/P9228 SAM88RCRI INSTRUCTION SET6-25JP — JumpJP cc,dst (Conditional)JP dst (Unconditional)Operation: If cc is true, PC ¨ dstThe condition

SAM88RI INSTRUCTION SET S3C9228/P92286-26JR — Jump RelativeJR cc,dstOperation: If cc is true, PC ¨ PC + dstIf the condition specified by the c

S3C9228/P9228 SAM88RCRI INSTRUCTION SET6-27LD — LoadLD dst,srcOperation: dst ¨ srcThe contents of the source are loaded into the destination. The s

SAM88RI INSTRUCTION SET S3C9228/P92286-28LD — LoadLD (Continued)Examples: Given: R0 = 01H, R1 = 0AH, register 00H = 01H, register 01H = 20H,register

S3C9228/P9228 SAM88RCRI INSTRUCTION SET6-29LDC/LDE — Load MemoryLDC/LDE dst,srcOperation: dst ¨ srcThis instruction loads a byte from program or da

SAM88RI INSTRUCTION SET S3C9228/P92286-30LDC/LDE — Load MemoryLDC/LDE (Continued)Examples: Given: R0 = 11H, R1 = 34H, R2 = 01H, R3 = 04H, R4 = 00H, R

S3C9228/P9228 SAM88RCRI INSTRUCTION SET6-31LDCD/LDED — Load Memory and DecrementLDCD/LDED dst,srcOperation: dst ¨ srcrr ¨ rr – 1These instruction

SAM88RI INSTRUCTION SET S3C9228/P92286-32LDCI/LDEI — Load Memory and IncrementLDCI/LDEI dst,srcOperation: dst ¨ srcrr ¨ rr + 1These instruction

S3C9228/P9228 SAM88RCRI INSTRUCTION SET6-33NOP — No OperationNOPOperation: No action is performed when the CPU executes this instruction. Typically,

S3C9228/P9228 ADDRESS SPACES2-12 ADDRESS SPACESOVERVIEWThe S3C9228/P9228 microcontroller has three kinds of address space:— Program memory (ROM)— Inte

SAM88RI INSTRUCTION SET S3C9228/P92286-34OR — Logical OROR dst,srcOperation: dst ¨ dst OR srcThe source operand is logically ORed with the destin

S3C9228/P9228 SAM88RCRI INSTRUCTION SET6-35POP — Pop From StackPOP dstOperation: dst ¨ @SPSP ¨ SP + 1The contents of the location addressed by

SAM88RI INSTRUCTION SET S3C9228/P92286-36PUSH — Push To StackPUSH srcOperation: SP ¨ SP – 1@SP ¨ srcA PUSH instruction decrements the stack poi

S3C9228/P9228 SAM88RCRI INSTRUCTION SET6-37RCF — Reset Carry FlagRCF RCFOperation: C ¨ 0The carry flag is cleared to logic zero, regardless of its

SAM88RI INSTRUCTION SET S3C9228/P92286-38RET — ReturnRETOperation: PC ¨ @SPSP ¨ SP + 2The RET instruction is normally used to return to the pre

S3C9228/P9228 SAM88RCRI INSTRUCTION SET6-39RL — Rotate LeftRL dstOperation: C ¨ dst (7)dst (0) ¨ dst (7)dst (n + 1) ¨ dst (n), n = 0–6The co

SAM88RI INSTRUCTION SET S3C9228/P92286-40RLC — Rotate Left Through CarryRLC dstOperation: dst (0) ¨ CC ¨ dst (7)dst (n + 1) ¨ dst (n), n = 0–

S3C9228/P9228 SAM88RCRI INSTRUCTION SET6-41RR — Rotate RightRR dstOperation: C ¨ dst (0)dst (7) ¨ dst (0)dst (n) ¨ dst (n + 1), n = 0–6The c

SAM88RI INSTRUCTION SET S3C9228/P92286-42RRC — Rotate Right Through CarryRRC dstOperation: dst (7) ¨ CC ¨ dst (0)dst (n) ¨ dst (n + 1), n = 0

S3C9228/P9228 SAM88RCRI INSTRUCTION SET6-43SBC — Subtract With CarrySBC dst,srcOperation: dst ¨ dst – src – cThe source operand, along with the

ADDRESS SPACES S3C9228/P92282-2PROGRAM MEMORY (ROM)Program memory (ROM) stores program code or table data. The S3C9228 has 8K bytes of mask-programabl

SAM88RI INSTRUCTION SET S3C9228/P92286-44SCF — Set Carry FlagSCFOperation: C ¨ 1The carry flag (C) is set to logic one, regardless of its previous

S3C9228/P9228 SAM88RCRI INSTRUCTION SET6-45SRA — Shift Right ArithmeticSRA dstOperation: dst (7) ¨ dst (7)C ¨ dst (0)dst (n) ¨ dst (n + 1), n

SAM88RI INSTRUCTION SET S3C9228/P92286-46STOP — Stop OperationSTOPOperation:The STOP instruction stops both the CPU clock and system clock and causes

S3C9228/P9228 SAM88RCRI INSTRUCTION SET6-47SUB — SubtractSUB dst,srcOperation: dst ¨ dst – srcThe source operand is subtracted from the destinatio

SAM88RI INSTRUCTION SET S3C9228/P92286-48TCM — Test Complement Under MaskTCM dst,srcOperation: (NOT dst) AND srcThis instruction tests selected bit

S3C9228/P9228 SAM88RCRI INSTRUCTION SET6-49TM — Test Under MaskTM dst,srcOperation: dst AND srcThis instruction tests selected bits in the destinat

SAM88RI INSTRUCTION SET S3C9228/P92286-50XOR — Logical Exclusive ORXOR dst,srcOperation: dst ¨ dst XOR srcThe source operand is logically exclusiv

S3C9228/P9228 CLOCK CIRCUITS7-17 CLOCK CIRCUITSOVERVIEWThe S3C9228 microcontroller has two oscillator circuits: a main clock, and a sub clock circuit.

CLOCK CIRCUITS S3C9228/P92287-2MAIN OSCILLATOR CIRCUITSXINXOUTFigure 7-1. Crystal/Ceramic OscillatorXINXOUTFigure 7-2. External OscillatorXINXOUTRFigu

S3C9228/P9228 CLOCK CIRCUITS7-3CLOCK STATUS DURING POWER-DOWN MODESThe two power-down modes, Stop mode and Idle mode, affect the system clock as follo

S3C9228/P9228 ADDRESS SPACES2-3REGISTER ARCHITECTUREThe upper 72 bytes of the S3C9228/P9228's internal register file are addressed as working reg

CLOCK CIRCUITS S3C9228/P92287-4SYSTEM CLOCK CONTROL REGISTER (CLKCON)The system clock control register, CLKCON, is located in address D4H. It is read/

S3C9228/P9228 CLOCK CIRCUITS7-5OSCILLATOR CONTROL REGISTER (OSCCON)The oscillator control register, OSCCON, is located in address D3H. It is read/writ

CLOCK CIRCUITS S3C9228/P92287-6SWITCHING THE CPU CLOCKData loadings in the oscillator control register, OSCCON, determine whether a main or a sub cloc

S3C9228/P9228 CLOCK CIRCUITS7-7STOP CONTROL REGISTER (STPCON)The STOP control register, STPCON, is located in address E0H. It is read/write addressabl

CLOCK CIRCUITS S3C9228/P92287-8NOTES

S3C9228/P9228 RESETRESET and POWER-DOWN8-18 RESETRESET and POWER-DOWNSYSTEM RESETOVERVIEWDuring a power-on reset, the voltage at VDD goes to High leve

RESETRESET and POWER-DOWN S3C9228/P92288-2POWER-DOWN MODESSTOP MODEStop mode is invoked by the instruction STOP. In Stop mode, the operation of the CP

S3C9228/P9228 RESETRESET and POWER-DOWN8-3Using an Internal Interrupt to Release Stop ModeAn internal interrupt, watch timer, can be used to release s

RESETRESET and POWER-DOWN S3C9228/P92288-4HARDWARE RESET RESET VALUESTable 8-1 list the values for CPU and system registers, peripheral control regist

S3C9228/P9228 RESETRESET and POWER-DOWN8-5Table 8-1. Register Values after RESET RESET (Continued)Register Name Mnemonic AddressBit Values after RESET

ADDRESS SPACES S3C9228/P92282-4COMMON WORKING REGISTER AREA (C0H–CFH)The SAM88RCRI register architecture provides an efficient method of working regis

RESETRESET and POWER-DOWN S3C9228/P92288-6NOTES

S3C9228/P9228 I/O PORTS9-19 I/O PORTSOVERVIEWThe S3C9228/P9228 microcontroller has seven bit-programmable I/O ports, P0-P6. Port 0 is 6-bit port, port

I/O PORTS S3C9228/P92289-2PORT DATA REGISTERSTable 9-2 gives you an overview of the register locations of all seven S3C9228 I/O port data registers. D

S3C9228/P9228 I/O PORTS9-3PORT 0Port 0 is an 6-bit I/O port with individually configurable pins. Port 0 pins are accessed directly by writing orreadin

I/O PORTS S3C9228/P92289-4Port 0 Control Register (P0CON)EBH, Page 0, R/W.7 .6 .5 .4 .3 .2 .1 .0MSB LSBP0.3/BUZ(INT)P0CON bit-pair pin configuration s

S3C9228/P9228 I/O PORTS9-5Port 0 Interrupt Pending Bits (INTPND1.3-.0)D6H, Page 0, R/W.7 .6 .5 .4 .3 .2 .1 .0MSB LSBINTPND1 bit configuration settings

I/O PORTS S3C9228/P92289-6PORT 1Port 1 is an 4-bit I/O port with individually configurable pins. Port 1 pins are accessed directly by writing orreadin

S3C9228/P9228 I/O PORTS9-7Port 1 Interrupt Control Register (P1INT)F1H, Page 0, R/W.7 .6 .5 .4 .3 .2 .1 .0MSB LSBNot usedP1INT bit configuration setti

I/O PORTS S3C9228/P92289-8Port 1 Interrupt Edge Selection Register (P1EDGE)F2H, Page 0, R/W.7 .6 .5 .4 .3 .2 .1 .0MSB LSBP1EDGE bit configuration sett

S3C9228/P9228 I/O PORTS9-9PORT 2Port 2 is an 4-bit I/O port with individually configurable pins. Port 2 pins are accessed directly by writing orreadin

S3C9228/P9228 ADDRESS SPACES2-5SYSTEM STACKS3C9-series microcontrollers use the system stack for subroutine calls and returns and to store data. The P

I/O PORTS S3C9228/P92289-10Port 2 Pull-up Control Register (P2PUR)F4H, Page 0, R/W.7 .6 .5 .4 .3 .2 .1 .0MSB LSBP2PUR bit configuration settings:01Ena

S3C9228/P9228 I/O PORTS9-11PORT 3Port 3 is an 2-bit I/O port with individually configurable pins. Port 3 pins are accessed directly by writing orreadi

I/O PORTS S3C9228/P92289-12Port 3 Interrupt Control Register (P3INT)F7H, Page 0, R/W.7 .6 .5 .4 .3 .2 .1 .0MSB LSBNot usedP3INT bit configuration sett

S3C9228/P9228 I/O PORTS9-13Port 3 Interrupt Edge Selection Register (P3EDGE)F8H, Page 0, R/W.7 .6 .5 .4 .3 .2 .1 .0MSB LSBP3EDGE bit configuration set

I/O PORTS S3C9228/P92289-14PORT 4Port 4 is an 8-bit I/O port with individually configurable pins. Port 4 pins are accessed directly by writing orreadi

S3C9228/P9228 I/O PORTS9-15PORT 5Port 5 is an 8-bit I/O port with individually configurable pins. Port 5 pins are accessed directly by writing orreadi

I/O PORTS S3C9228/P92289-16PORT 6Port 6 is an 4-bit I/O port with individually configurable pins. Port 6 pins are accessed directly by writing orreadi

S3C9228/P9228 (Preliminary Spec) BASIC TIMER10-110 BASIC TIMEROVERVIEWBasic timer (BT) can be used in two different ways:— As a watchdog timer to prov

BASIC TIMER S3C9228/P9228 (Preliminary Spec)10-2BASIC TIMER CONTROL REGISTER (BTCON)The basic timer control register, BTCON, is used to select the inp

S3C9228/P9228 (Preliminary Spec) BASIC TIMER10-3BASIC TIMER FUNCTION DESCRIPTIONWatchdog Timer FunctionYou can program the basic timer overflow signal

S3C9228/P9228 MICROCONTROLLERS iiiPrefaceThe S3C9228/P9228 Microcontrollers User's Manual is designed for application designers and programmers w

ADDRESS SPACES S3C9228/P92282-6++ PROGRAMMING TIP — Standard Stack Operations Using PUSH and POPThe following example shows you how to perform stack o

BASIC TIMER S3C9228/P9228 (Preliminary Spec)10-4NOTE: During a power-on reset operation, the CPU is idle during the required oscillationstabilization

S3C9228/P9228 TIMER 111-111 TIMER 1ONE 16-BIT TIMER MODE (TIMER 1)The 16-bit timer 1 is used in one 16-bit timer or two 8-bit timers mode. If TACON.7

TIMER 1 S3C9228/P922811-2Timer 1 Control Register (TACON)You use the timer 1 control register, TACON, to— Enable the timer 1 operating (interval timer

S3C9228/P9228 TIMER 111-3NOTE: When one 16-bit timer mode (TACON.7 <- "1": Timer 1)TACON.6-.4MUX1/81/641/2561/512INTPND2.0TAOUTT1INT1/1DI

TIMER 1 S3C9228/P922811-4TWO 8-BIT TIMERS MODE (TIMER A and B)OVERVIEWThe 8-bit timer A and B are the 8-bit general-purpose timers. Timer A and B have

S3C9228/P9228 TIMER 111-5TACON and TBCON are located in page 0, at address BBH and BAH, and is read/write addressable usingregister addressing mode.A

TIMER 1 S3C9228/P922811-6Timer B Control Register (TBCON)BAH, R/W.7 .6 .5 .4 .3 .2 .1 .0MSB LSBTimer B match interrupt enable bit:0 = Disable match i

S3C9228/P9228 TIMER 111-7FUNCTION DESCRIPTIONInterval Timer Function (Timer A and Timer B)The timer A and B module can generate an interrupt: the time

TIMER 1 S3C9228/P922811-8NOTE: When two 8-bit timers mode (TACON.7 <- "0": Timer A)TACON.6-.4MUX1/81/641/2561/512INTPND2.0TAOUTTAINTDIVRf

S3C9228/P9228 TIMER 111-91/11/81/641/2561/512NOTE: When two 8-bit timers mode (TACON.7 <- "0": Timer B)TBCON.6-.4MUXINTPND2.1TBINTDIVRfxt

S3C9228/P9228 ADDRESSING MODES3-13 ADDRESSING MODESOVERVIEWInstructions that are stored in program memory are fetched for execution using the program

TIMER 1 S3C9228/P922811-10NOTES

S3C9228/P9228 WATCH TIMER12-112 WATCH TIMEROVERVIEWWatch timer functions include real-time and watch-time measurement and interval timing for the syst

WATCH TIMER S3C9228/P922812-2WATCH TIMER CONTROL REGISTER (WTCON)The watch timer control register, WTCON is used to select the input clock source, th

S3C9228/P9228 WATCH TIMER12-3WATCH TIMER CIRCUIT DIAGRAMWT INT EnableWTCON.1WTCON.2WTCON.3WTCON.4WTCON.5WTCON.6Enable/DisableSelectorCircuitMUXINTPND2

WATCH TIMER S3C9228/P922812-4NOTES

S3C9228/P9228 LCD CONTROLLER/DRIVER13-113 LCD CONTROLLER/DRIVEROVERVIEWThe S3C9228/P9228 microcontroller can directly drive an up-to-128-dot (16segmen

LCD CONTROLLER/DRIVER S3C9228/P922813-2LCD CIRCUIT DIAGRAMSEG15/P5.3COM4/SEG19/P5.7COM7/SEG16/P5.416016Data BUSPortLatchLPOTDisplayRAM(Page1)PortLatch

S3C9228/P9228 LCD CONTROLLER/DRIVER13-3LCD RAM ADDRESS AREARAM addresses of page 1 are used as LCD data memory. When the bit value of a display segmen

LCD CONTROLLER/DRIVER S3C9228/P922813-4LCD MODE CONTROL REGISTER (LMOD)A LMOD is located in page 0, at address FEH, and is read/write addressable usin

S3C9228/P9228 LCD CONTROLLER/DRIVER13-5LCD PORT CONTROL REGISTERThe LCD port control register LPOT is used to control LCD signal pins or normal I/O pi

ADDRESSING MODES S3C9228/P92283-2REGISTER ADDRESSING MODE (R)In Register addressing mode, the operand is the content of a specified register (see Figu

LCD CONTROLLER/DRIVER S3C9228/P922813-6LCD VOLTAGE DIVIDING RESISTORS1/5 BiasS3C9228/P9228VDDRRRRRLMOD.4VLC1VLC2VLC3VLC4VLC5VSS1/4 BiasS3C9228/P9228VD

S3C9228/P9228 LCD CONTROLLER/DRIVER13-71 FrameFRVDDVSSCOM0COM1COM2COM3COM4COM5COM6COM7COM1 VLC2 (VLC3)VLC4VSSVDDVLC1SEG0 VLC2 (VLC3)VLC4VSSVDDVLC1COM2

LCD CONTROLLER/DRIVER S3C9228/P922813-81 FrameVDDVSS0 1 230 1 23COM1VSSVDDVLC1(VLC2)VLC3(VLC4)COM2VSSVDDVLC1(VLC2)VLC3(VLC4)COM3VSSVDDVLC1(VLC2)VLC3(V

S3C9228/P9228 LCD CONTROLLER/DRIVER13-91 FrameVDDVSS012COM1VSSVDDVLC1(VLC2)VLC3(VLC4)COM2VSSVDDVLC1(VLC2)VLC3(VLC4)SEG0VSSVDDVLC1(VLC2)VLC3(VLC4)SEG1V

LCD CONTROLLER/DRIVER S3C9228/P922813-10NOTES

S3C9228/P9228 A/D CONVERTER14-114 10-BIT ANALOG-TO-DIGITAL CONVERTEROVERVIEWThe 10-bit A/D converter (ADC) module uses successive approximation logic

A/D CONVERTER S3C9228/P922814-2CONVERSION TIMINGThe A/D conversion process requires 4 steps (4 clock edges) to convert each bit and 10 clocks to set-

S3C9228/P9228 A/D CONVERTER14-3Conversion Data Register ADDATAH/ADDATALD1H/D2H, Page 0, Read Only.9 .8 .7 .6 .5 .4 .3 .2MSB LSB (ADDATAH)- - - - - - .

A/D CONVERTER S3C9228/P922814-4S3C9228AD0-AD3AnalogInput PinVDD101C(VSS ≤ ADC input ≤ VDD)Figure 14-4. Recommended A/D Converter Circuit for Highest

S3C9228/P9228 SERIAL I/O INTERFACE15-115 SERIAL I/O INTERFACEOVERVIEWSerial I/O modules, SIO can interface with various types of external device that

S3C9228/P9228 ADDRESSING MODES3-3INDIRECT REGISTER ADDRESSING MODE (IR)In Indirect Register (IR) addressing mode, the content of the specified registe

SERIAL I/O INTERFACE S3C9228/P922815-2SIO CONTROL REGISTERS (SIOCON)The control register for serial I/O interface module, SIOCON, is located at E1H in

S3C9228/P9228 SERIAL I/O INTERFACE15-3SIO PRE-SCALER REGISTER (SIOPS)The prescaler register for serial I/O interface module, SIOPS, are located at E3H

SERIAL I/O INTERFACE S3C9228/P922815-4SERIAL I/O TIMING DIAGRAM (SIO)SOTransmitCompleteSIO INTSet SIOCON.3DO7 DO6 DO5 DO4 DO3 DO2 DO1 DO0DI7 DI6 DI5 D

S3C9228/P9228 ELECTRICAL DATA16-116 ELECTRICAL DATAOVERVIEWIn this chapter, S3C9228/P9228 electrical characteristics are presented in tables and graph

ELECTRICAL DATA S3C9228/P922816-2Table 16-1. Absolute Maximum Ratings(TA = 25°C)Parameter Symbol Conditions Rating UnitSupply voltageVDD– – 0.3 to +

S3C9228/P9228 ELECTRICAL DATA16-3Table 16-2. D.C. Electrical Characteristics (Continued)(TA = – 25°C to + 85°C, VDD = 2.0 V to 5.5 V)Parameter

ELECTRICAL DATA S3C9228/P922816-4Table 16-2. D.C. Electrical Characteristics (Concluded)(TA = – 25°C to + 85°C, VDD = 2.0 V to 5.5 V)Parameter

S3C9228/P9228 ELECTRICAL DATA16-5Table 16-3. Data Retention Supply Voltage in Stop Mode(TA = – 25 °C to + 85 °C)Parameter Symbol Conditions Min Ty

ELECTRICAL DATA S3C9228/P922816-6Execution ofSTOP InstrctionRESETOccurs~~VDDDR~~Stop ModeOscillationStabilizationTImeNormalOperating ModeData Retentio

S3C9228/P9228 ELECTRICAL DATA16-7Table 16-5. A.C. Electrical Characteristics(TA = – 25°C to + 85°C, VDD = 2.0 V to 5.5 V)Parameter Symbol Condit

ADDRESSING MODES S3C9228/P92283-4INDIRECT REGISTER ADDRESSING MODE (Continued)dstOPCODEPAIRPoints toRigister PairExampleInstructionReferencesProgramMe

ELECTRICAL DATA S3C9228/P922816-8Table 16-6. A/D Converter Electrical Characteristics(TA = – 25°C to + 85°C, VDD = 2.7 V to 5.5 V, VSS = 0 V)Par

S3C9228/P9228 ELECTRICAL DATA16-9RESETtRSL0.2 VDDFigure 16-4. Input Timing for RESETRESETtKHtKL0.2VDDSCKtKCY0.8VDD0.8VDD0.2VDDtSIKtKSISISOtKSOOutput D

ELECTRICAL DATA S3C9228/P922816-10Table 16-7. Main Oscillation Characteristics (TA = – 25°C to + 85°C)Oscillator Clock Configuration Parameter Te

S3C9228/P9228 ELECTRICAL DATA16-11Table 16-9. Main Oscillation Stabilization Time(TA = – 25 °C to + 85 °C, VDD = 2.0 V to 5.5 V)Oscillator Test

ELECTRICAL DATA S3C9228/P922816-12Table 16-10. Sub Oscillation Stabilization Time(TA = – 25 °C to + 85 °C, VDD = 2.0 V to 5.5 V)Oscillator Test

S3C9228/P9228 ELECTRICAL DATA16-13 2 MHz6.25 kHz (main)/8.2 kHz(sub)1 2 6Supply Voltage (V)Instruction Clock = 1/4n x oscillator frequency (n = 1, 2,

ELECTRICAL DATA S3C9228/P922816-14NOTES

S3C9228/P9228 MECHANICAL DATA17-117 MECHANICAL DATAOVERVIEWThe S3C9228/P9228 microcontroller is currently available in a 42-pin SDIP and 44-pin QFP pa

MECHANICAL DATA S3C9228/P922817-244-QFP-1010B#44NOTE: Dimensions are in millimeters.10.00 ± 0.213.20 ± 0.310.00 ± 0.213.20 ± 0.3#10.35+ 0.10- 0.050.

S3C9228/P9228 S3P9228 OTP 18-118 S3P9228 OTPOVERVIEWThe S3P9228 single-chip CMOS microcontroller is the OTP (One Time Programmable) version of the S3

S3C9228/P9228 ADDRESSING MODES3-5INDIRECT REGISTER ADDRESSING MODE (Continued)dstOPCODEOPERAND4-BitWorkingRegisterAddressPoint to theWoking Register(1

S3P9228 OTP S3C9228/P922818-2 COM1/P6.2COM0/P6.3P0.0/TAOUT/INTP0.1/T1CLK/INTP0.2/INTP0.3/BUZ/INTP1.0/AD0/INTP1.1/AD1/INTSDAT/P1.2/AD2/INTSCLK/P1.3/AD

S3C9228/P9228 S3P9228 OTP 18-3Table 18-1. Descriptions of Pins Used to Read/Write the EPROMMain Chip During ProgrammingPin Name Pin Name Pin No. I/O

S3P9228 OTP S3C9228/P922818-4 Table 18-4. D.C. Electrical Characteristics(TA = – 25°C to + 85°C, VDD = 2.0 V to 5.5 V)Parameter Symbol Condit

S3C9228/P9228 S3P9228 OTP 18-52 MHz6.25 kHz (main)/8.2 kHz(sub)1 2 6Supply Voltage (V)Instruction Clock = 1/4n x oscillator frequency (n = 1, 2, 8, 1

S3P9228 OTP S3C9228/P922818-6 NOTES

S3C9228/P9228 DEVELOPMENT TOOLS19-119 DEVELOPMENT TOOLSOVERVIEWSamsung provides a powerful and easy-to-use development support system in turn key form

DEVELOPMENT TOOLS S3C9228/P922819-2BUSSMDS2+RS-232CPODProbeAdapterPROM/OTP Writer UnitRAM Break/Display UnitTrace/Timer UnitSAM8 Base UnitPower Suppl

S3C9228/P9228 DEVELOPMENT TOOLS19-3TB9228 TARGET BOARDThe TB9228 target board is used for the S3C9228 microcontroller. It is supported by the SMDS2+ d

DEVELOPMENT TOOLS S3C9228/P922819-4Table 19-1. Power Selection Settings for TB9228"To User_VCC"SettingsOperating Mode CommentsTo User_VCCOf

S3C9228/P9228 DEVELOPMENT TOOLS19-5SMDS2+ Selection (SAM8)In order to write data into program memory that is available in SMDS2+, the target board sho

ADDRESSING MODES S3C9228/P92283-6INDIRECT REGISTER ADDRESSING MODE (Concluded)dstOPCODE4-Bit WorkingRegister AddressSample Instructions:LCD R5,@RR6 ;

DEVELOPMENT TOOLS S3C9228/P922819-6J10142-SDIPJ10244-QFP1234567891011121314151617181920214344454642414039383736353433323130292827262524232250494847P6

S3C9228/P9228 DEVELOPMENT TOOLS19-7 Target Board Target SystemTarget Cable for ConnectorPart Name: AP42SDOrder Code: SM6538J1011 4221 22J1011 4221 225

DEVELOPMENT TOOLS S3C9228/P922819-8NOTES

S3C9228/P9228 ADDRESSING MODES3-7INDEXED ADDRESSING MODE (X)Indexed (X) addressing mode adds an offset value to a base address during instruction exec

ADDRESSING MODES S3C9228/P92283-8INDEXED ADDRESSING MODE (Continued)Point to WorkingRegister Pair(1 of 8)LSB Selects16-Bitaddressadded tooffsetdstOPCO

S3C9228/P9228 ADDRESSING MODES3-9INDEXED ADDRESSING MODE (Concluded)Point to WorkingRegister Pair(1 of 8)LSB Selects16-Bitaddressadded tooffsetProgram

ADDRESSING MODES S3C9228/P92283-10DIRECT ADDRESS MODE (DA)In Direct Address (DA) mode, the instruction provides the operand's 16-bit memory addre

S3C9228/P9228 ADDRESSING MODES3-11DIRECT ADDRESS MODE (Continued)OPCODEProgram MemoryUpper Address ByteProgramMemoryAddressUsedLower Address ByteSampl

ADDRESSING MODES S3C9228/P92283-12RELATIVE ADDRESS MODE (RA)In Relative Address (RA) mode, a two's-complement signed displacement between – 128

S3C9228/P9228 CONTROL REGISTERS4-14 CONTROL REGISTERSOVERVIEWIn this section, detailed descriptions of the S3C9228/P9228 control registers are present

CONTROL REGISTERS S3C9228/P92284-2Table 4-1. System and Peripheral Control Registers (Page 0)Register Name Mnemonic Address (Page 0) R/WDecimal HexPor

S3C9228/P9228 CONTROL REGISTERS4-3Table 4-1. System and Peripheral Control Registers (Page 0)Register Name Mnemonic Address (Page 0) R/WDecimal HexLoc

CONTROL REGISTERS S3C9228/P92284-4FLAGS - System Flags Register.7.6.5Bit IdentifierRESET RESET ValueRead/WriteR = Read-onlyW = Write-onlyR/W = Read/wr

S3C9228/P9228 CONTROL REGISTERS4-5ADCON — A/D Converter Control Register D0HBit Identifier .7 .6 .5 .4 .3 .2 .1 .0RESETRESET Value– – 0 0 0 0 0 0Read/

CONTROL REGISTERS S3C9228/P92284-6BTCON — Basic Timer Control Register DCHBit Identifier .7 .6 .5 .4 .3 .2 .1 .0RESETRESET Value0 0 0 0 0 0 0 0Read/Wr

S3C9228/P9228 CONTROL REGISTERS4-7CLKCON — System Clock Control Register D4HBit Identifier .7 .6 .5 .4 .3 .2 .1 .0RESETRESET Value0 0 0 0 0 0 0 0Re

S3C9228/P9228 MICROCONTROLLERS vTable of ContentsPart I — Programming ModelChapter 1 Product OverviewSAM88RCRI Product Family ...

CONTROL REGISTERS S3C9228/P92284-8FLAGS — System Flags Register D5HBit Identifier .7 .6 .5 .4 .3 .2 .1 .0RESETRESET Valuex x x x – – – –Read/WriteR/W

S3C9228/P9228 CONTROL REGISTERS4-9INTPND1 — Interrupt Pending Register 1 D6HBit Identifier .7 .6 .5 .4 .3 .2 .1 .0RESETRESET Value0 0 0 0 0 0 0 0Read/

CONTROL REGISTERS S3C9228/P92284-10INTPND2 — Interrupt Pending Register 2 D7HBit Identifier .7 .6 .5 .4 .3 .2 .1 .0RESETRESET Value– – 0 0 0 0 0 0Read

S3C9228/P9228 CONTROL REGISTERS4-11LMOD — LCD Mode Control Register FEHBit Identifier .7 .6 .5 .4 .3 .2 .1 .0RESETRESET Value– 0 0 0 0 0 0 0Read/Write

CONTROL REGISTERS S3C9228/P92284-12LPOT — LCD Port Control Register D8HBit Identifier .7 .6 .5 .4 .3 .2 .1 .0RESETRESET Value– 0 0 0 0 0 0 0Read/Write

S3C9228/P9228 CONTROL REGISTERS4-13OSCCON — Oscillator Control Register D3HBit Identifier .7 .6 .5 .4 .3 .2 .1 .0RESETRESET Value– – – – 0 0 – 0Read

CONTROL REGISTERS S3C9228/P92284-14P0CON – Port 0 Control Register EBHBit Identifier .7 .6 .5 .4 .3 .2 .1 .0RESETRESET Value0 0 0 0

S3C9228/P9228 CONTROL REGISTERS4-15P0INT –Port 0 Interrupt Enable Register EDHBit Identifier .7 .6 .5 .4 .3 .2 .1 .0RESETRESET Value– – – – 0 0 0 0R

CONTROL REGISTERS S3C9228/P92284-16P0PUR –Port 0 Pull-up Resistors Enable Register ECHBit Identifier .7 .6 .5 .4 .3 .2 .1 .0RESETRESET Value– – – –

S3C9228/P9228 CONTROL REGISTERS4-17P0EDGE –Port 0 Interrupt Edge Selection Register EEHBit Identifier .7 .6 .5 .4 .3 .2 .1 .0RESETRESET Value– – – –

vi S3C9228/P9228 MICROCONTROLLERSTable of Contents (Continued)Chapter 4 Control RegistersOverview ...

CONTROL REGISTERS S3C9228/P92284-18P1CON – Port 1 Control Register EFHBit Identifier .7 .6 .5 .4 .3 .2 .1 .0RESETRESET Value0 0 0 0

S3C9228/P9228 CONTROL REGISTERS4-19P1INT –Port 1 Interrupt Enable Register F1HBit Identifier .7 .6 .5 .4 .3 .2 .1 .0RESETRESET Value– – – – 0 0 0 0R

CONTROL REGISTERS S3C9228/P92284-20P1PUR –Port 1 Pull-up Resistors Enable Register F0HBit Identifier .7 .6 .5 .4 .3 .2 .1 .0RESETRESET Value– – – –

S3C9228/P9228 CONTROL REGISTERS4-21P1EDGE –Port 1 Interrupt Edge Selection Register F2HBit Identifier .7 .6 .5 .4 .3 .2 .1 .0RESETRESET Value– – – –

CONTROL REGISTERS S3C9228/P92284-22P2CON – Port 2 Control Register F3HBit Identifier .7 .6 .5 .4 .3 .2 .1 .0RESETRESET Value0 0 0 0

S3C9228/P9228 CONTROL REGISTERS4-23P2PUR –Port 2 Pull-up Resistors Enable Register F4HBit Identifier .7 .6 .5 .4 .3 .2 .1 .0RESETRESET Value– – – –

CONTROL REGISTERS S3C9228/P92284-24P3CON – Port 3 Control Register F5HBit Identifier .7 .6 .5 .4 .3 .2 .1 .0RESETRESET Value– – – –

S3C9228/P9228 CONTROL REGISTERS4-25P3INT –Port 3 Interrupt Enable Register F7HBit Identifier .7 .6 .5 .4 .3 .2 .1 .0RESETRESET Value– – – – – – 0 0R

CONTROL REGISTERS S3C9228/P92284-26P3PUR –Port 3 Pull-up Resistors Enable Register F6HBit Identifier .7 .6 .5 .4 .3 .2 .1 .0RESETRESET Value– – – –

S3C9228/P9228 CONTROL REGISTERS4-27P3EDGE –Port 3 Interrupt Edge Selection Register F8HBit Identifier .7 .6 .5 .4 .3 .2 .1 .0RESETRESET Value– – – –

S3C9228/P9228 MICROCONTROLLERS viiTable of Contents (Continued)Part II — Hardware DescriptionsChapter 7 Clock CircuitOverview...

CONTROL REGISTERS S3C9228/P92284-28P4CONH – Port 4 Control Register High Byte F9HBit Identifier .7 .6 .5 .4 .3 .2 .1 .0RESETRESET Val

S3C9228/P9228 CONTROL REGISTERS4-29P4CONL–Port 4 Control Register Low Byte FAHBit Identifier .7 .6 .5 .4 .3 .2 .1 .0RESETRESET Value0 0 0 0 0 0 0 0R

CONTROL REGISTERS S3C9228/P92284-30P5CONH – Port 5 Control Register High Byte FBHBit Identifier .7 .6 .5 .4 .3 .2 .1 .0RESETRESET Value0 0 0 0 0 0 0

S3C9228/P9228 CONTROL REGISTERS4-31P5CONL – Port 5 Control Register Low Byte FCHBit Identifier .7 .6 .5 .4 .3 .2 .1 .0RESETRESET Value0 0 0 0 0 0 0

CONTROL REGISTERS S3C9228/P92284-32P6CON – Port 6 Control Register High Byte FDHBit Identifier .7 .6 .5 .4 .3 .2 .1 .0RESETRESET Value0 0 0 0 0 0 0

S3C9228/P9228 CONTROL REGISTERS4-33SIOCON — SIO Control Register E1HBit Identifier .7 .6 .5 .4 .3 .2 .1 .0RESETRESET Value0 0 0 0 0 0 0 –Read/WriteR/W

CONTROL REGISTERS S3C9228/P92284-34STPCON – Stop Control Register E0HBit Identifier .7 .6 .5 .4 .3 .2 .1 .0RESETRESET Value0 0 0 0 0 0 0 0Read/Write

S3C9228/P9228 CONTROL REGISTERS4-35SYM — System Mode Register DFHBit Identifier.7.6 .5 .4 .3 .2 .1 .0RESETRESET Value– – – – 0 0 0 0Read/Write– – – –

CONTROL REGISTERS S3C9228/P92284-36TACON — Timer 1/A Control Register BBHBit Identifier .7 .6 .5 .4 .3 .2 .1 .0RESETRESET Value0 0 0 0 0 0 0 –Read/Wri

S3C9228/P9228 CONTROL REGISTERS4-37TBCON — Timer B Control Register BAHBit Identifier .7 .6 .5 .4 .3 .2 .1 .0RESETRESET Value– 0 0 0 0 0 0 –Read/Write

viii S3C9228/P9228 MICROCONTROLLERSTable of Contents (Continued)Chapter 11 Timer 1One 16-Bit Timer Mode (Timer 1) ...

CONTROL REGISTERS S3C9228/P92284-38WTCON — Watch Timer Control Register DAHBit Identifier .7 .6 .5 .4 .3 .2 .1 .0RESETRESET Value0 0 0 0 0 0 0 –Read/W

S3C9228/P9228 INTERRUPT STRUCTURE5-15 INTERRUPT STRUCTUREOVERVIEWThe SAM88RCRI interrupt structure has two basic components: a vector, and sources. Th

INTERRUPT STRUCTURE S3C9228/P92285-2INTERRUPT PENDING FUNCTION TYPESWhen the interrupt service routine has executed, the application program's se

S3C9228/P9228 INTERRUPT STRUCTURE5-3INTERRUPT SOURCE SERVICE SEQUENCEThe interrupt request polling and servicing sequence is as follows:1. A source ge

INTERRUPT STRUCTURE S3C9228/P92285-4S3C9228/P9228 INTERRUPT STRUCTUREThe S3C9228/P9228 microcontroller has fourteen peripheral interrupt sources:— Tim

S3C9228/P9228 INTERRUPT STRUCTURE5-5SYM.3(EI, DI)P0INT.0P0.0 External InterriptP0INT.1P0.1 External InterriptP0.3 External InterriptP0.2 External Inte

INTERRUPT STRUCTURE S3C9228/P92285-6Programming Tip — How to clear an interrupt pending bitAs the following examples are shown, a load instruction sho

S3C9228/P9228 SAM88RCRI INSTRUCTION SET6-16 SAM88RCRI INSTRUCTION SETOVERVIEWThe SAM88RCRI instruction set is designed to support the large register f

SAM88RI INSTRUCTION SET S3C9228/P92286-2Table 6-1. Instruction Group SummaryMnemonic Operands InstructionLoad InstructionsCLR dst ClearLD dst,src Load

S3C9228/P9228 SAM88RCRI INSTRUCTION SET6-3Table 6-1. Instruction Group Summary (Continued)Mnemonic Operands InstructionProgram Control InstructionsCAL