Samsung S3C2440A User Manual

S3C2440A 32-BIT RISC MICROPROCESSOR USER'S MANUAL PRELIMINARY Revision 0.14 (June 30, 2004)

S3C2440A RISC MICROPROCESSOR PRODUCT OVERVIEW 1-9 Table 1-1. 289-Pin FBGA Pin Assignments – Pin Number Order (Sheet 3 of 3) Pin Number Pin Name

S3C2440A RISC MICROPROCESSOR ARM INSTRUCTION SET 3-43 Rn1R1R12R53R1R54R7Rn0x100C0x10000x0FF40x100C0x10000x0FF40x100C0x10000x0FF40x100C0x10000x0F

ARM INSTRUCTION SET S3C2440A RISC MICROPROCESSOR 3-44 INCLUSION OF THE BASE IN THE REGISTER LIST When write-back is specified, the base is writt

S3C2440A RISC MICROPROCESSOR ARM INSTRUCTION SET 3-45 ASSEMBLER SYNTAX <LDM|STM>{cond}<FD|ED|FA|EA|IA|IB|DA|DB> Rn{!},<Rlist>{

ARM INSTRUCTION SET S3C2440A RISC MICROPROCESSOR 3-46 EXAMPLES LDMFD SP!,{R0,R1,R2} ; Unstack 3 registers. STMIA R0,{R0-R15} ; Save al

S3C2440A RISC MICROPROCESSOR ARM INSTRUCTION SET 3-47 SINGLE DATA SWAP (SWP) 31 19 15Cond28 16 11122123B2000 Rn Rd[3:0] Source Register[15:12] D

ARM INSTRUCTION SET S3C2440A RISC MICROPROCESSOR 3-48 USE OF R15 Do not use R15 as an operand (Rd, Rn or Rs) in a SWP instruction. DATA ABORTS

S3C2440A RISC MICROPROCESSOR ARM INSTRUCTION SET 3-49 SOFTWARE INTERRUPT (SWI) The instruction is only executed if the condition is true. The va

ARM INSTRUCTION SET S3C2440A RISC MICROPROCESSOR 3-50 ASSEMBLER SYNTAX SWI{cond} <expression> {cond} Two character condition mnemoni

S3C2440A RISC MICROPROCESSOR ARM INSTRUCTION SET 3-51 COPROCESSOR DATA OPERATIONS (CDP) The instruction is only executed if the condition is tru

ARM INSTRUCTION SET S3C2440A RISC MICROPROCESSOR 3-52 INSTRUCTION CYCLE TIMES Coprocessor data operations take 1S + bI incremental cycles to exe

PRODUCT OVERVIEW S3C2440A RISC MICROPROCESSOR 1-10 Table 1-2. S3C2440A 289-Pin FBGA Pin Assignments (Sheet 1 of 9) Pin Number Pin Name Default F

S3C2440A RISC MICROPROCESSOR ARM INSTRUCTION SET 3-53 COPROCESSOR DATA TRANSFERS (LDC, STC) The instruction is only executed if the condition is

ARM INSTRUCTION SET S3C2440A RISC MICROPROCESSOR 3-54 THE COPROCESSOR FIELDS The CP# field is used to identify the coprocessor which is required

S3C2440A RISC MICROPROCESSOR ARM INSTRUCTION SET 3-55 ASSEMBLER SYNTAX <LDC|STC>{cond}{L} p#,cd,<Address> LDC Load from memory

ARM INSTRUCTION SET S3C2440A RISC MICROPROCESSOR 3-56 COPROCESSOR REGISTER TRANSFERS (MRC, MCR) The instruction is only executed if the conditio

S3C2440A RISC MICROPROCESSOR ARM INSTRUCTION SET 3-57 TRANSFERS TO R15 When a coprocessor register transfer to ARM920T has R15 as the destinatio

ARM INSTRUCTION SET S3C2440A RISC MICROPROCESSOR 3-58 UNDEFINED INSTRUCTION The instruction is only executed if the condition is true. The vario

S3C2440A RISC MICROPROCESSOR ARM INSTRUCTION SET 3-59 INSTRUCTION SET EXAMPLES The following examples show ways in which the basic ARM920T instr

ARM INSTRUCTION SET S3C2440A RISC MICROPROCESSOR 3-60 Division and Remainder A number of divide routines for specific applications are provided

S3C2440A RISC MICROPROCESSOR ARM INSTRUCTION SET 3-61 5. Overflow in unsigned multiply accumulate with a 64 bit result UMULL Rl,Rh,Rm,Rn ;

ARM INSTRUCTION SET S3C2440A RISC MICROPROCESSOR 3-62 Multiplication by 6 ADD Ra,Ra,Ra,LSL #1 ; Multiply by 3 MOV Ra,Ra,LSL#1 ; and th

S3C2440A RISC MICROPROCESSOR PRODUCT OVERVIEW 1-11 Table 1-2. S3C2440A 289-Pin FBGA Pin Assignments (Sheet 2 of 9) Pin Number Pin Name Default F

S3C2440A RISC MICROPROCESSOR ARM INSTRUCTION SET 3-63 LOADING A WORD FROM AN UNKNOWN ALIGNMENT ; Enter with address in Ra (32 bits) uses

ARM INSTRUCTION SET S3C2440A RISC MICROPROCESSOR 3-64 NOTES

S3C2440A RISC MICROPROCESSOR THUMB INSTRUCTION SET 4-1 4 THUMB INSTRUCTION SET THUMB INSTRUCTION SET FORMAT The thumb instruction sets are 16-bi

THUMB INSTRUCTION SET S3C2440A RISC MICROPROCESSOR 4-2 FORMAT SUMMARY The THUMB instruction set formats are shown in the following figure. Move

S3C2440A RISC MICROPROCESSOR THUMB INSTRUCTION SET 4-3 OPCODE SUMMARY The following table summarizes the THUMB instruction set. For further infor

THUMB INSTRUCTION SET S3C2440A RISC MICROPROCESSOR 4-4 Table 4-1. THUMB Instruction Set Opcodes (Continued) Mnemonic Instruction Lo-Register Op

S3C2440A RISC MICROPROCESSOR THUMB INSTRUCTION SET 4-5 FORMAT 1: MOVE SHIFTED REGISTER 15 001410[2:0] Destination Register[5:3] Source Register

THUMB INSTRUCTION SET S3C2440A RISC MICROPROCESSOR 4-6 INSTRUCTION CYCLE TIMES All instructions in this format have an equivalent ARM instructi

S3C2440A RISC MICROPROCESSOR THUMB INSTRUCTION SET 4-7 FORMAT 2: ADD/SUBTRACT 15014 10[2:0] Destination Register[5:3] Source Register [8:6] Reg

THUMB INSTRUCTION SET S3C2440A RISC MICROPROCESSOR 4-8 INSTRUCTION CYCLE TIMES All instructions in this format have an equivalent ARM instructi

PRODUCT OVERVIEW S3C2440A RISC MICROPROCESSOR 1-12 Table 1-2. S3C2440A 289-Pin FBGA Pin Assignments (Sheet 3 of 9) Pin Number Pin Name Default F

S3C2440A RISC MICROPROCESSOR THUMB INSTRUCTION SET 4-9 FORMAT 3: MOVE/COMPARE/ADD/SUBTRACT IMMEDIATE 15 0014 10[7:0] Immediate Vale[10:8] Source/

THUMB INSTRUCTION SET S3C2440A RISC MICROPROCESSOR 4-10 INSTRUCTION CYCLE TIMES All instructions in this format have an equivalent ARM instruct

S3C2440A RISC MICROPROCESSOR THUMB INSTRUCTION SET 4-11 FORMAT 4: ALU OPERATIONS 15 001410[2:0] Source/Destination Register[5:3] Source Register

THUMB INSTRUCTION SET S3C2440A RISC MICROPROCESSOR 4-12 INSTRUCTION CYCLE TIMES All instructions in this format have an equivalent ARM instruct

S3C2440A RISC MICROPROCESSOR THUMB INSTRUCTION SET 4-13 FORMAT 5: HI-REGISTER OPERATIONS/BRANCH EXCHANGE 15 001410[2:0] Destination Register[5:3]

THUMB INSTRUCTION SET S3C2440A RISC MICROPROCESSOR 4-14 Table 4-6. Summary of Format 5 Instructions (Continued) Op H1 H2 THUMB assembler AR

S3C2440A RISC MICROPROCESSOR THUMB INSTRUCTION SET 4-15 EXAMPLES Hi-Register Operations ADD PC, R5 ; PC := PC + R5 but don't set the co

THUMB INSTRUCTION SET S3C2440A RISC MICROPROCESSOR 4-16 FORMAT 6: PC-RELATIVE LOAD 15 001410[7:0] Immediate Value[10:8] Destination RegisterWor

S3C2440A RISC MICROPROCESSOR THUMB INSTRUCTION SET 4-17 INSTRUCTION CYCLE TIMES All instructions in this format have an equivalent ARM instructio

THUMB INSTRUCTION SET S3C2440A RISC MICROPROCESSOR 4-18 FORMAT 7: LOAD/STORE WITH REGISTER OFFSET [2:0] Source/Destination Register[5:3] Base R

S3C2440A RISC MICROPROCESSOR PRODUCT OVERVIEW 1-13 Table 1-2. S3C2440A 289-Pin FBGA Pin Assignments (Sheet 4 of 9) Pin Number Pin Name Default F

S3C2440A RISC MICROPROCESSOR THUMB INSTRUCTION SET 4-19 OPERATION These instructions transfer byte or word values between registers and memory. M

THUMB INSTRUCTION SET S3C2440A RISC MICROPROCESSOR 4-20 FORMAT 8: LOAD/STORE SIGN-EXTENDED BYTE/HALFWORD [2:0] Destination Register[5:3] Base R

S3C2440A RISC MICROPROCESSOR THUMB INSTRUCTION SET 4-21 INSTRUCTION CYCLE TIMES All instructions in this format have an equivalent ARM instructio

THUMB INSTRUCTION SET S3C2440A RISC MICROPROCESSOR 4-22 FORMAT 9: LOAD/STORE WITH IMMEDIATE OFFSET [2:0] Source/Destination Register[5:3] Base

S3C2440A RISC MICROPROCESSOR THUMB INSTRUCTION SET 4-23 OPERATION These instructions transfer byte or word values between registers and memory us

THUMB INSTRUCTION SET S3C2440A RISC MICROPROCESSOR 4-24 FORMAT 10: LOAD/STORE HALFWORD [2:0] Source/Destination Register[5:3] Base Register [

S3C2440A RISC MICROPROCESSOR THUMB INSTRUCTION SET 4-25 INSTRUCTION CYCLE TIMES All instructions in this format have an equivalent ARM instructio

THUMB INSTRUCTION SET S3C2440A RISC MICROPROCESSOR 4-26 FORMAT 11: SP-RELATIVE LOAD/STORE [7:0] Immediate Value[10:8] Destination Register [1

S3C2440A RISC MICROPROCESSOR THUMB INSTRUCTION SET 4-27 INSTRUCTION CYCLE TIMES All instructions in this format have an equivalent ARM instructio

THUMB INSTRUCTION SET S3C2440A RISC MICROPROCESSOR 4-28 FORMAT 12: LOAD ADDRESS [7:0] 8-bit Unsigned Constant[10:8] Destination Register [11]

PRODUCT OVERVIEW S3C2440A RISC MICROPROCESSOR 1-14 Table 1-2. S3C2440A 289-Pin FBGA Pin Assignments (Sheet 5 of 9) Pin Number Pin Name Default F

S3C2440A RISC MICROPROCESSOR THUMB INSTRUCTION SET 4-29 INSTRUCTION CYCLE TIMES All instructions in this format have an equivalent ARM instructio

THUMB INSTRUCTION SET S3C2440A RISC MICROPROCESSOR 4-30 FORMAT 13: ADD OFFSET TO STACK POINTER [6:0] 7-bit Immediate Value[7] Sign Flag0 = Offs

S3C2440A RISC MICROPROCESSOR THUMB INSTRUCTION SET 4-31 FORMAT 14: PUSH/POP REGISTERS [7:0] Register List[8] PC/LR Bit0 = Do not store LR/Load PC

THUMB INSTRUCTION SET S3C2440A RISC MICROPROCESSOR 4-32 INSTRUCTION CYCLE TIMES All instructions in this format have an equivalent ARM instruct

S3C2440A RISC MICROPROCESSOR THUMB INSTRUCTION SET 4-33 FORMAT 15: MULTIPLE LOAD/STORE [7:0] Register List[10:8] Base Register[11] Load/Store Bit

THUMB INSTRUCTION SET S3C2440A RISC MICROPROCESSOR 4-34 FORMAT 16: CONDITIONAL BRANCH [7:0] 8-bit Signed Immediate[11:8] Condition15 01141013 1

S3C2440A RISC MICROPROCESSOR THUMB INSTRUCTION SET 4-35 Table 4-17. The Conditional Branch Instructions (Continued) L THUMB assembler ARM equiv

THUMB INSTRUCTION SET S3C2440A RISC MICROPROCESSOR 4-36 FORMAT 17: SOFTWARE INTERRUPT [7:0] Comment Field15 01141013 1211Value 817810 91111 Fig

S3C2440A RISC MICROPROCESSOR THUMB INSTRUCTION SET 4-37 FORMAT 18: UNCONDITIONAL BRANCH [10:0] Immediate Value15 01141113 1211Offset110100 Figure

THUMB INSTRUCTION SET S3C2440A RISC MICROPROCESSOR 4-38 FORMAT 19: LONG BRANCH WITH LINK [10:0] Long Branch and Link Offset High/Low[11] Low/Hi

S3C2440A RISC MICROPROCESSOR PRODUCT OVERVIEW 1-15 Table 1-2. S3C2440A 289-Pin FBGA Pin Assignments (Sheet 6 of 9) Pin Number Pin Name Default F

S3C2440A RISC MICROPROCESSOR THUMB INSTRUCTION SET 4-39 INSTRUCTION CYCLE TIMES This instruction format does not have an equivalent ARM instructi

THUMB INSTRUCTION SET S3C2440A RISC MICROPROCESSOR 4-40 INSTRUCTION SET EXAMPLES The following examples show ways in which the THUMB instructio

S3C2440A RISC MICROPROCESSOR THUMB INSTRUCTION SET 4-41 GENERAL PURPOSE SIGNED DIVIDE This example shows a general purpose signed divide and rema

THUMB INSTRUCTION SET S3C2440A RISC MICROPROCESSOR 4-42 Now fix up the signs of the quotient (R0) and remainder (R1) POP {R2, R3} ; Get di

S3C2440A RISC MICROPROCESSOR THUMB INSTRUCTION SET 4-43 DIVISION BY A CONSTANT Division by a constant can often be performed by a short fixed seq

THUMB INSTRUCTION SET S3C2440A RISC MICROPROCESSOR 4-44 NOTES

S3C2440A RISC MICROPROCESSOR MEMORY CONTROLLER 5-1 5 MEMORY CONTROLLER OVERVIEW The S3C2440A memor

MEMORY CONTROLLER S3C2440A RISC MICROPROCESSOR 5-2 0x0000_00000x0800_00000x1000_00000x1800_00000x2000_00000x2800_00000x300

S3C2440A RISC MICROPROCESSOR MEMORY CONTROLLER DEC.13, 2002 5-3 FUNCTION DESCRIPTION BANK0 BUS WIDT

MEMORY CONTROLLER S3C2440A RISC MICROPROCESSOR 5-4 SDRAM BANK ADDRESS PIN CONNECTION EXAMPLE Table 5-2. SDRAM Bank Address

PRODUCT OVERVIEW S3C2440A RISC MICROPROCESSOR 1-16 Table 1-2. S3C2440A 289-Pin FBGA Pin Assignments (Sheet 7 of 9) Pin Number Pin Name Default F

S3C2440A RISC MICROPROCESSOR MEMORY CONTROLLER DEC.13, 2002 5-5 nWAIT PIN OPERATION If the WAIT bit

MEMORY CONTROLLER S3C2440A RISC MICROPROCESSOR 5-6 nXBREQ/nXBACK Pin Operation If nXBREQ is asserted, the S3C2440A will res

S3C2440A RISC MICROPROCESSOR MEMORY CONTROLLER DEC.13, 2002 5-7 ROM Memory Interface Examples A0A1A

MEMORY CONTROLLER S3C2440A RISC MICROPROCESSOR 5-8 A2A3A4A5A6A7A8A9A10A11A12A13A14A15A16A17A0A1A2A3A4A5A6A7A8A9A10A11A12A13

S3C2440A RISC MICROPROCESSOR MEMORY CONTROLLER DEC.13, 2002 5-9 SRAM Memory Interface Examples A1A2

MEMORY CONTROLLER S3C2440A RISC MICROPROCESSOR 5-10 SDRAM Memory Interface Examples A1A2A3A4A5A6A7A8A9A10A11A12D0D1D2D3D4D5

S3C2440A RISC MICROPROCESSOR MEMORY CONTROLLER DEC.13, 2002 5-11 PROGRAMMABLE ACCESS CYCLE TcohTcos

MEMORY CONTROLLER S3C2440A RISC MICROPROCESSOR 5-12 MCLKSCKEnSCSnSCASADDRA10/APRAnSRASBADATA (CL2)DATA (CL3)nWEDQMTrpTrcd

S3C2440A RISC MICROPROCESSOR MEMORY CONTROLLER DEC.13, 2002 5-13 BUS WIDTH & WAIT CONTROL REGIS

MEMORY CONTROLLER S3C2440A RISC MICROPROCESSOR 5-14 BUS WIDTH & WAIT CONTROL REGISTER (BWSCON) (Continued) WS2 [10] D

S3C2440A RISC MICROPROCESSOR PRODUCT OVERVIEW 1-17 Table 1-2. S3C2440A 289-Pin FBGA Pin Assignments (Sheet 8 of 9) Pin Number Pin Name Default F

S3C2440A RISC MICROPROCESSOR MEMORY CONTROLLER DEC.13, 2002 5-15 BANK CONTROL REGISTER (BANKCONn: n

MEMORY CONTROLLER S3C2440A RISC MICROPROCESSOR 5-16 BANK CONTROL REGISTER (BANKCONn: nGCS6-nGCS7) Register Address R/W De

S3C2440A RISC MICROPROCESSOR MEMORY CONTROLLER DEC.13, 2002 5-17 REFRESH CONTROL REGISTER Register

MEMORY CONTROLLER S3C2440A RISC MICROPROCESSOR 5-18 BANKSIZE REGISTER Register Address R/W Description Reset Value BANKS

S3C2440A RISC MICROPROCESSOR MEMORY CONTROLLER DEC.13, 2002 5-19 SDRAM MODE REGISTER SET REGISTER (

MEMORY CONTROLLER S3C2440A RISC MICROPROCESSOR 5-20 NOTES

S3C2440A RISC MICROPROCESSOR NAND FLASH CONTROLLER

NAND FLASH CONTROLLER S3C2440A RISC MICROPROCESSOR 6-2 BLOCK DIAGRAM zmyljjGnUzGzO[riGzyhtPzGzjSYSTEM BUSuhukGmsh

S3C2440A RISC MICROPROCESSOR NAND FLASH CONTROLLER

NAND FLASH CONTROLLER S3C2440A RISC MICROPROCESSOR 6-4 NAND FLASH MEMORY TIMING HCLKCLE / ALEnWETACLS TWRPH0 TWRPH1DATACOMMAND / ADDRESS Figure 6-3

PRODUCT OVERVIEW S3C2440A RISC MICROPROCESSOR 1-18 Table 1-2. S3C2440A 289-Pin FBGA Pin Assignments (Sheet 9 of 9) Pin Number Pin Name Default F

S3C2440A RISC MICROPROCESSOR NAND FLASH CONTROLLER

NAND FLASH CONTROLLER S3C2440A RISC MICROPROCESSOR 6-6 Data Register Configuration 1) 16-bit NAND Flash Memory Interface A. Word Access Register

S3C2440A RISC MICROPROCESSOR NAND FLASH CONTROLLER

NAND FLASH CONTROLLER S3C2440A RISC MICROPROCESSOR 6-8 ECC MODULE FEATURES ECC generation is controlled by the ECC Lock (MainECCLock, SpareECCLock)

S3C2440A RISC MICROPROCESSOR NAND FLASH CONTROLLER

NAND FLASH CONTROLLER S3C2440A RISC MICROPROCESSOR 6-10 NAND FLASH MEMORY CONFIGURATION I/O7I/O6I/O5I/O4I/O3I/O2I/O1I/O0R/ BWEALECLECERERnBnFWEALEC

S3C2440A RISC MICROPROCESSOR NAND FLASH CONTROLLER

NAND FLASH CONTROLLER S3C2440A RISC MICROPROCESSOR 6-12 AdvFlash (Read only) [3] Advance NAND flash memory for auto-booting 0: Support 256 or

S3C2440A RISC MICROPROCESSOR NAND FLASH CONTROLLER

NAND FLASH CONTROLLER S3C2440A RISC MICROPROCESSOR 6-14 0: Unlock Spare ECC 1: Lock Spare ECC Spare area ECC status register is NFSECC(0x4E00003

S3C2440A RISC MICROPROCESSOR PRODUCT OVERVIEW 1-1 1 PRODUCT OVERVIEW INTRODUCTION This user’s manual describes

S3C2440A RISC MICROPROCESSOR PRODUCT OVERVIEW 1-19 NOTE: 1. The @BUS REQ. shows the pin state at the external bus, which is used by the other

S3C2440A RISC MICROPROCESSOR NAND FLASH CONTROLLER

NAND FLASH CONTROLLER S3C2440A RISC MICROPROCESSOR 6-16 MAIN DATA AREA REGISTER Register Address R/W Description Reset ValueNFMECCD0 0x4E00001

S3C2440A RISC MICROPROCESSOR NAND FLASH CONTROLLER

NAND FLASH CONTROLLER S3C2440A RISC MICROPROCESSOR 6-18 NFCON STATUS REGISTER Register Address R/W Description Reset ValueNFSTAT 0x4E000020 R/

S3C2440A RISC MICROPROCESSOR NAND FLASH CONTROLLER

NAND FLASH CONTROLLER S3C2440A RISC MICROPROCESSOR 6-20 MAIN DATA AREA ECC0 STATUS REGISTER Register Address R/W Description Reset ValueNFMECC0

S3C2440A RISC MICROPROCESSOR NAND FLASH CONTROLLER

NAND FLASH CONTROLLER S3C2440A RISC MICROPROCESSOR 6-22 The NFSLK and NFEBLK can be changed while Soft lock bit(NFCONT[12]) is enabled. But cannot

S3C2440A RISC MICROPROCESSOR CLOCK & POWER MANAGEMENT 7-1 7 CLOCK & POWER MANAGEMENT OVERVIEW The Clock & Power mana

CLOCK & POWER MANAGEMENT S3C2440A RISC MICROPROCESSOR 7-2 FUNCTIONAL DESCRIPTION CLOCK ARCHITECTURE Figure 7-1 shows a block diagram of the

PRODUCT OVERVIEW S3C2440A RISC MICROPROCESSOR 1-20 THE TABLE BELOW SHOWS I/O TYPES AND DESCRIPTIONS. Input (I)/Output (O) Type Descriptions d

S3C2440A RISC MICROPROCESSOR CLOCK & POWER MANAGEMENT 7-3 Nand FlashControllerOSCMPLLUPLLCLKCNTLFCLKHDIVN PDIVNMpllControlSi

CLOCK & POWER MANAGEMENT S3C2440A RISC MICROPROCESSOR 7-4 PHASE LOCKED LOOP (PLL) The MPLL within the clock generator, as a circuit, synchro

S3C2440A RISC MICROPROCESSOR CLOCK & POWER MANAGEMENT 7-5 DividerPLoop FilterFinM[7:0]S[1:0]PFDDividerMP[5:0]FvcoPUMPVCODivi

CLOCK & POWER MANAGEMENT S3C2440A RISC MICROPROCESSOR 7-6 CLOCK CONTROL LOGIC The Clock Control Logic determines the clock source to be used

S3C2440A RISC MICROPROCESSOR CLOCK & POWER MANAGEMENT 7-7 Change PLL Settings In Normal Operation Mode During the operation

CLOCK & POWER MANAGEMENT S3C2440A RISC MICROPROCESSOR 7-8 FCLK, HCLK, and PCLK FCLK is used by ARM920T. HCLK is used for AHB bus, which is

S3C2440A RISC MICROPROCESSOR CLOCK & POWER MANAGEMENT 7-9 NOTE 1. CLKDIVN should be set carefully not to exceed the limit o

CLOCK & POWER MANAGEMENT S3C2440A RISC MICROPROCESSOR 7-10 POWER MANAGEMENT The Power Management block controls the system clocks by softwar

S3C2440A RISC MICROPROCESSOR CLOCK & POWER MANAGEMENT 7-11 IDLESLEEPNORMAL(SLOW_BIT=0)SLOW(SLOW_BIT=1)IDLE_BIT=1Interrupts,

CLOCK & POWER MANAGEMENT S3C2440A RISC MICROPROCESSOR 7-12 NORMAL Mode In Normal mode, all peripherals and the basic blocks including power

S3C2440A RISC MICROPROCESSOR PRODUCT OVERVIEW 1-21 SIGNAL DESCRIPTIONS Table 1-3. S3C2440A Signal Descriptions (Sheet 1 of 6) Signal Input/Outpu

S3C2440A RISC MICROPROCESSOR CLOCK & POWER MANAGEMENT 7-13 Users can change the frequency by enabling SLOW mode bit in CLKSL

CLOCK & POWER MANAGEMENT S3C2440A RISC MICROPROCESSOR 7-14 If the user switches from SLOW mode to Normal mode by disabling SLOW_BIT and MPLL

S3C2440A RISC MICROPROCESSOR CLOCK & POWER MANAGEMENT 7-15 SLEEP Mode The block disconnects the internal power. So, there oc

CLOCK & POWER MANAGEMENT S3C2440A RISC MICROPROCESSOR 7-16 Follow the Procedure to Wake-up from SLEEP mode 1. The internal reset signal wil

S3C2440A RISC MICROPROCESSOR CLOCK & POWER MANAGEMENT 7-17 Power Control of VDDi and VDDiarm In SLEEP mode, VDDi, VDDiarm, V

CLOCK & POWER MANAGEMENT S3C2440A RISC MICROPROCESSOR 7-18 Signaling EINT[15:0] for Wakeup The S3C2440A can be woken up from SLEEP mode only

S3C2440A RISC MICROPROCESSOR CLOCK & POWER MANAGEMENT 7-19 Output Port State and SLEEP Mode The output port should have a p

CLOCK & POWER MANAGEMENT S3C2440A RISC MICROPROCESSOR 7-20 CLOCK GENERATOR & POWER MANAGEMENT SPECIAL REGISTER LOCK TIME COUNT REGISTER

S3C2440A RISC MICROPROCESSOR CLOCK & POWER MANAGEMENT 7-21 PLL CONTROL REGISTER (MPLLCON & UPLLCON) Register Address R/W

CLOCK & POWER MANAGEMENT S3C2440A RISC MICROPROCESSOR 7-22 CLOCK CONTROL REGISTER (CLKCON) Register Address R/W Description Reset Value CL

PRODUCT OVERVIEW S3C2440A RISC MICROPROCESSOR 1-22 Table 1-3. S3C2440A Signal Descriptions (Sheet 2 of 6) Signal Input/Output Descriptions LCD

S3C2440A RISC MICROPROCESSOR CLOCK & POWER MANAGEMENT 7-23 CLOCK SLOW CONTROL (CLKSLOW) REGISTER Register Address R/W Descr

CLOCK & POWER MANAGEMENT S3C2440A RISC MICROPROCESSOR 7-24 CLOCK DIVIDER CONTROL (CLKDIVN) REGISTER Register Address R/W Description Reset

S3C2440A RISC MICROPROCESSOR CLOCK & POWER MANAGEMENT 7-25 CAMERA CLOCK DIVIDER (CAMDIVN) REGISTER Register Address R/W De

S3C2440A RISC MICROPROCESSOR

DMA S3C2440A RISC MICROPROCESSOR 8-2 DMA REQUEST SOURCES Each channel of the DMA controller can select one of the DMA reque

S3C2440A RISC MICROPROCESSOR

DMA S3C2440A RISC MICROPROCESSOR 8-4 Demand/Handshake Mode Comparison Demand and Handshake modes are related to the protoco

S3C2440A RISC MICROPROCESSOR

DMA S3C2440A RISC MICROPROCESSOR 8-6 EXAMPLES Single service in Demand Mode with Unit Transfer Size The assertion of XnXDRE

S3C2440A RISC MICROPROCESSOR

S3C2440A RISC MICROPROCESSOR PRODUCT OVERVIEW 1-23 Table 1-3. S3C2440A Signal Descriptions (Sheet 3 of 6) Signal Input/Output Descriptions UAR

DMA S3C2440A RISC MICROPROCESSOR 8-8 DMA INITIAL DESTINATION (DIDST) REGISTER Register Address R/W Description Reset Valu

S3C2440A RISC MICROPROCESSOR

DMA S3C2440A RISC MICROPROCESSOR 8-10 DCONn Bit Description Initial StateSERVMODE [27] Select the service mode between

S3C2440A RISC MICROPROCESSOR

DMA S3C2440A RISC MICROPROCESSOR 8-12 DMA CURRENT SOURCE (DCSRC) REGISTER Register Address R/W Description Reset Value DC

S3C2440A RISC MICROPROCESSOR

DMA S3C2440A RISC MICROPROCESSOR 8-14 NOTES

S3C2440A RISC MICROPROCESSOR I/O PORTS 9-1 9 I/O PORTS OVERVIEW S3C2440A has 130 multi-functional input/output port pins and there are eight po

I/O PORTS S3C2440A RISC MICROPROCESSOR 9-2 Table 9-1. S3C2440A Port Configuration(Sheet 1 of 5) Port A Selectable Pin Functions GPA22 Output o

S3C2440A RISC MICROPROCESSOR I/O PORTS 9-3 Table 9-1. S3C2440A Port Configuration(Sheet 2 of 5) Port B Selectable Pin Functions GPB10 Input/o

PRODUCT OVERVIEW S3C2440A RISC MICROPROCESSOR 1-24 Table 1-3. S3C2440A Signal Descriptions (Sheet 4 of 6) Signal Input/Output Description SPI

I/O PORTS S3C2440A RISC MICROPROCESSOR 9-4 Table 9-1. S3C2440A Port Configuration(Sheet 3 of 5) Port D Selectable Pin Functions GPD15 Input/ou

S3C2440A RISC MICROPROCESSOR I/O PORTS 9-5 Table 9-1. S3C2440A Port Configuration(Sheet 4 of 5) Port F Selectable Pin Functions GPF7 Input/ou

I/O PORTS S3C2440A RISC MICROPROCESSOR 9-6 Table 9-1. S3C2440A Port Configuration(Sheet 5 of 5) Port H Selectable Pin Functions GPH10 Input/ou

S3C2440A RISC MICROPROCESSOR I/O PORTS 9-7 PORT CONTROL DESCRIPTIONS PORT CONFIGURATION REGISTER (GPACON-GPJCON) In S3C2440A, most of the pins

I/O PORTS S3C2440A RISC MICROPROCESSOR 9-8 I/O PORT CONTROL REGISTER PORT A CONTROL REGISTERS(GPACON, GPADAT) Register Address R/W Description

S3C2440A RISC MICROPROCESSOR I/O PORTS 9-9 GPADAT Bit Description GPA[24:0] [24:0] When the port is configured as output port, the pin sta

I/O PORTS S3C2440A RISC MICROPROCESSOR 9-10 PORT B CONTROL REGISTERS(GPBCON, GPBDAT, GPBUP) Register Address R/W Description Reset Value GPB

S3C2440A RISC MICROPROCESSOR I/O PORTS 9-11 PORT C CONTROL REGISTERS(GPCCON, GPCDAT, GPCUP) Register Address R/W Description Reset Value GPC

I/O PORTS S3C2440A RISC MICROPROCESSOR 9-12 GPCDAT Bit Description GPC[15:0] [15:0] When the port is configured as input port, the correspo

S3C2440A RISC MICROPROCESSOR I/O PORTS 9-13 PORT D CONTROL REGISTERS(GPDCON, GPDDAT, GPDUP) Register Address R/W Description Reset Value GPD

S3C2440A RISC MICROPROCESSOR PRODUCT OVERVIEW 1-25 Table 1-3. S3C2440A Signal Descriptions (Sheet 5 of 6) Signal Input/Output Description Rese

I/O PORTS S3C2440A RISC MICROPROCESSOR 9-14 GPDDAT Bit Description GPD[15:0] [15:0] When the port is configured as input port, the correspo

S3C2440A RISC MICROPROCESSOR I/O PORTS 9-15 PORT E CONTROL REGISTERS(GPECON, GPEDAT, GPEUP) Register Address R/W Description Reset Value GPE

I/O PORTS S3C2440A RISC MICROPROCESSOR 9-16 . GPEDAT Bit Description GPE[15:0] [15:0] When the port is configured as an input port, the corr

S3C2440A RISC MICROPROCESSOR I/O PORTS 9-17 PORT F CONTROL REGISTERS(GPFCON, GPFDAT) If GPF0 - GPF7 will be used for wake-up signals at power

I/O PORTS S3C2440A RISC MICROPROCESSOR 9-18 PORT G CONTROL REGISTERS(GPGCON, GPGDAT) If GPG0 - GPG7 will be used for wake-up signals at Sleep m

S3C2440A RISC MICROPROCESSOR I/O PORTS 9-19 GPGDAT Bit Description GPG[15:0] [15:0] When the port is configured as an input port, the corr

I/O PORTS S3C2440A RISC MICROPROCESSOR 9-20 PORT H CONTROL REGISTERS(GPHCON, GPHDAT) Register Address R/W Description Reset Value GPHCON 0x5

S3C2440A RISC MICROPROCESSOR I/O PORTS 9-21 GPHDAT Bit Description GPH[10:0] [10:0] When the port is configured as an input port, the corr

I/O PORTS S3C2440A RISC MICROPROCESSOR 9-22 PORT J CONTROL REGISTERS(GPJCON, GPJDAT) Register Address R/W Description Reset Value GPJCON 0x5

S3C2440A RISC MICROPROCESSOR I/O PORTS 9-23 GPJDAT Bit Description GPJ15:0] [12:0] When the port is configured as an input port, the corre

PRODUCT OVERVIEW S3C2440A RISC MICROPROCESSOR 1-26 Table 1-3. S3C2440A Signal Descriptions (Sheet 6 of 6) Signal Input/Output Description Power

I/O PORTS S3C2440A RISC MICROPROCESSOR 9-24 MISCELLANEOUS control register(MISCCR) In Sleep mode, the data bus(D[31:0] or D[15:0] can be set as

S3C2440A RISC MICROPROCESSOR I/O PORTS 9-25 CLKSEL1(1) [10:8] Select source clock with CLKOUT1 pad 000 = MPLL output 001 = UPLL output 010 =

I/O PORTS S3C2440A RISC MICROPROCESSOR 9-26 DCLK CONTROL REGISTERS(DCLKCON) Register Address R/W Description Reset Value DCLKCON 0x56000084

S3C2440A RISC MICROPROCESSOR I/O PORTS 9-27 EXTINTn(External Interrupt Control Register n) The 8 external interrupts can be requested by vari

I/O PORTS S3C2440A RISC MICROPROCESSOR 9-28 EXTINT1 Bit Description FLTEN15 [31] Filter Enable for EINT15 0 = Filter Disable 1= Filter E

S3C2440A RISC MICROPROCESSOR I/O PORTS 9-29 EXTINT2 Bit Description Reset ValueFLTEN23 [31] Filter Enable for EINT23 0 = Filter Disable

I/O PORTS S3C2440A RISC MICROPROCESSOR 9-30 EINT17 [6:4] Setting the signaling method of the EINT17. 000 = Low level 001 = High level 01x

S3C2440A RISC MICROPROCESSOR I/O PORTS 9-31 EINTFLTn(External Interrupt Filter Register n) To recognize the level interrupt, the valid logic

I/O PORTS S3C2440A RISC MICROPROCESSOR 9-32 EINTMASK(External Interrupt Mask Register) Register Address R/W Description Reset Value EINTMASK

S3C2440A RISC MICROPROCESSOR I/O PORTS 9-33 EINTPEND(External Interrupt Pending Register) Register Address R/W Description Reset Value EINTP

S3C2440A RISC MICROPROCESSOR PRODUCT OVERVIEW 1-27 S3C2440A SPECIAL REGISTERS Table 1-4. S3C2440A Special Registers (Sheet 1 of 14) Register Na

I/O PORTS S3C2440A RISC MICROPROCESSOR 9-34 EINT5 [5] It is cleard by writing “1” 0 = not occur 1= occur interrupt 0 EINT4 [4] It is

S3C2440A RISC MICROPROCESSOR I/O PORTS 9-35 GSTATUSn (General Status Registers) Register Address R/W Description Reset Value GSTATUS0 0x560

I/O PORTS S3C2440A RISC MICROPROCESSOR 9-36 DSCn (Drive Strength Control) Control the Memory I/O drive strength Register Address R/W Descripti

S3C2440A RISC MICROPROCESSOR I/O PORTS 9-37 DSC1 Bit Description Reset Value DSC_SCK1 [29:28] SCLK1 Drive strength. 00: 12mA 10: 10mA

I/O PORTS S3C2440A RISC MICROPROCESSOR 9-38 MSLCON (Memory Sleep Control Register) Select memory interface status when in SLEEP mode. Register

S3C2440A RISC MICROPROCESSOR PWM TIMER 10-1 10 PWM TIMER OVERVIEW The S3C2440A has five 16-bit timer

PWM TIMER S3C2440A RISC MICROPROCESSOR 10-2 ClockDivider5:1 MUXDead ZoneGeneratorTOUT0TOUT1TOUT2ControlLogic0TCMPB0 TCNTB0C

S3C2440A RISC MICROPROCESSOR PWM TIMER 10-3 PWM TIMER OPERATION PRESCALER & DIVIDER An 8-bit pres

PWM TIMER S3C2440A RISC MICROPROCESSOR 10-4 AUTO RELOAD & DOUBLE BUFFERING S3C2440A PWM Timers have a double buffering

S3C2440A RISC MICROPROCESSOR PWM TIMER 10-5 TIMER INITIALIZATION USING MANUAL UPDATE BIT AND INVERTER

PRODUCT OVERVIEW S3C2440A RISC MICROPROCESSOR 1-28 Table 1-4. S3C2440A Special Registers (Sheet 2 of 14) Register Name Address (B. Endian) Addr

PWM TIMER S3C2440A RISC MICROPROCESSOR 10-6 TIMER OPERATION TOUTn12 4650 110 4040 60203 79 105 8 11 Figure 10-4. Example of

S3C2440A RISC MICROPROCESSOR PWM TIMER 10-7 PULSE WIDTH MODULATION (PWM) WriteTCMPBn = 60WriteTCMPBn

PWM TIMER S3C2440A RISC MICROPROCESSOR 10-8 OUTPUT LEVEL CONTROL Inverter offInitial State Period 1 Period 2 Timer StopInve

S3C2440A RISC MICROPROCESSOR PWM TIMER 10-9 DEAD ZONE GENERATOR The Dead Zone is for the PWM control

PWM TIMER S3C2440A RISC MICROPROCESSOR 10-10 DMA REQUEST MODE The PWM timer can generate a DMA request at every specific ti

S3C2440A RISC MICROPROCESSOR PWM TIMER 10-11 PWM TIMER CONTROL REGISTERS TIMER CONFIGURATION REGISTER

PWM TIMER S3C2440A RISC MICROPROCESSOR 10-12 TIMER CONFIGURATION REGISTER1 (TCFG1) Register Address R/W Description Reset

S3C2440A RISC MICROPROCESSOR PWM TIMER 10-13 TIMER CONTROL (TCON) REGISTER Register Address R/W Desc

PWM TIMER S3C2440A RISC MICROPROCESSOR 10-14 TCON (Continued) TCON Bit Description Initial stateReserved [7:5] Reserved

S3C2440A RISC MICROPROCESSOR PWM TIMER 10-15 TIMER 0 COUNT BUFFER REGISTER & COMPARE BUFFER REGIS

PRODUCT OVERVIEW S3C2440A RISC MICROPROCESSOR 1-2 FEATURES Architecture • Integrated system for hand-held devices and general embedded applicat

S3C2440A RISC MICROPROCESSOR PRODUCT OVERVIEW 1-29 Table 1-4. S3C2440A Special Registers (Sheet 3 of 14) Register Name Address (B. Endian) Addr

PWM TIMER S3C2440A RISC MICROPROCESSOR 10-16 TIMER 1 COUNT BUFFER REGISTER & COMPARE BUFFER REGISTER (TCNTB1/TCMPB1) Re

S3C2440A RISC MICROPROCESSOR PWM TIMER 10-17 TIMER 2 COUNT BUFFER REGISTER & COMPARE BUFFER REGIS

PWM TIMER S3C2440A RISC MICROPROCESSOR 10-18 TIMER 3 COUNT BUFFER REGISTER & COMPARE BUFFER REGISTER (TCNTB3/TCMPB3) Re

S3C2440A RISC MICROPROCESSOR PWM TIMER 10-19 TIMER 4 COUNT BUFFER REGISTER (TCNTB4) Register Address

PWM TIMER S3C2440A RISC MICROPROCESSOR 10-20 NOTES

S3C2440A RISC MICROPROCESSOR UART 11-1 11 UART OVERVIEW The S3C2440A Universal Asynchronous Receiver

UART S3C2440A RISC MICROPROCESSOR 11-2 BLOCK DIAGRAM Buad-rateGeneratorControlUnitTransmitterReceiverPeripheral BUSTXDnClock

S3C2440A RISC MICROPROCESSOR UART 11-3 UART OPERATION The following sections describe the UART opera

UART S3C2440A RISC MICROPROCESSOR 11-4 Auto Flow Control (AFC) The S3C2440A's UART 0 and UART 1 support auto flow contr

S3C2440A RISC MICROPROCESSOR UART 11-5 RS-232C interface If the user wants to connect the UART to m

PRODUCT OVERVIEW S3C2440A RISC MICROPROCESSOR 1-30 Table 1-4. S3C2440A Special Registers (Sheet 4 of 14) Register Name Address (B. Endian) Addr

UART S3C2440A RISC MICROPROCESSOR 11-6 UART Error Status FIFO UART has the error status FIFO besides the Rx FIFO register. T

S3C2440A RISC MICROPROCESSOR UART 11-7 Baud-rate Generation Each UART's baud-rate generator pro

UART S3C2440A RISC MICROPROCESSOR 11-8 Infrared (IR) Mode The S3C2440A UART block supports infrared (IR) transmission and re

S3C2440A RISC MICROPROCESSOR UART 11-9 StartBitStopBitData BitsSIO Frame0101001101 Figure 11-4. Seri

UART S3C2440A RISC MICROPROCESSOR 11-10 UART SPECIAL REGISTERS UART LINE CONTROL REGISTER There are three UART line control

S3C2440A RISC MICROPROCESSOR UART 11-11 UART CONTROL REGISTER There are three UART control registers

UART S3C2440A RISC MICROPROCESSOR 11-12 Tx Interrupt Type [9] Interrupt request type. 0 = Pulse (Interrupt is requested a

S3C2440A RISC MICROPROCESSOR UART 11-13 UART CONTROL REGISTER (Continued) Transmit Mode [3:2] Dete

UART S3C2440A RISC MICROPROCESSOR 11-14 UART FIFO CONTROL REGISTER There are three UART FIFO control registers including UFC

S3C2440A RISC MICROPROCESSOR UART 11-15 UART MODEM CONTROL REGISTER There are two UART MODEM control

S3C2440A RISC MICROPROCESSOR PRODUCT OVERVIEW 1-31 Table 1-4. S3C2440A Special Registers (Sheet 5 of 14) Register Name Address (B. Endian) Addr

UART S3C2440A RISC MICROPROCESSOR 11-16 UART TX/RX STATUS REGISTER There are three UART Tx/Rx status registers including UTR

S3C2440A RISC MICROPROCESSOR UART 11-17 UART ERROR STATUS REGISTER There are three UART Rx error sta

UART S3C2440A RISC MICROPROCESSOR 11-18 UART FIFO STATUS REGISTER There are three UART FIFO status registers including UFSTA

S3C2440A RISC MICROPROCESSOR UART 11-19 UART MODEM STATUS REGISTER There are two UART modem status r

UART S3C2440A RISC MICROPROCESSOR 11-20 UART TRANSMIT BUFFER REGISTER (HOLDING REGISTER & FIFO REGISTER) There are three

S3C2440A RISC MICROPROCESSOR UART 11-21 UART BAUD RATE DIVISOR REGISTER There are three UART baud ra

UART S3C2440A RISC MICROPROCESSOR 11-22 NOTES

S3C2440A RISC MICROPROCESSOR USB HOST 12-1 12 USB HOST CONTROLLER OVERVIEW S3C2440A supports 2-port USB

USB HOST S3C2440A RISC MICROPROCESSOR 12-2 USB HOST CONTROLLER SPECIAL REGISTERS The S3C2440A USB host controller complies with OHCI Rev 1.0.

S3C2440A RISC MICROPROCESSOR USB DEVICE 13-1 13 USB DEVICE CONTROLLER OVERVIEW Universal Serial Bus

PRODUCT OVERVIEW S3C2440A RISC MICROPROCESSOR 1-32 Table 1-4. S3C2440A Special Registers (Sheet 6 of 14) Register Name Address (B. Endian) Addr

USB DEVICE S3C2440A RISC MICROPROCESSOR 13-2 SIERT_VP_OUTRT_VM_INRT_VP_INRXDRT_UXSUSPENDRT_UX_OENRT_VM_OUTMC_ADDR[13:0]SIUGF

S3C2440A RISC MICROPROCESSOR USB DEVICE 13-3 USB DEVICE CONTROLLER SPECIAL REGISTERS This section de

USB DEVICE S3C2440A RISC MICROPROCESSOR 13-4 EP2_DMA_CON Endpoint2 DMA control register 0x218(L) / 0x21B(B)EP2_DMA_UNIT

S3C2440A RISC MICROPROCESSOR USB DEVICE 13-5 FUNCTION ADDRESS REGISTER (FUNC_ADDR_REG) This register

USB DEVICE S3C2440A RISC MICROPROCESSOR 13-6 POWER MANAGEMENT REGISTER (PWR_REG) This register acts as a power control regis

S3C2440A RISC MICROPROCESSOR USB DEVICE 13-7 INTERRUPT REGISTER (EP_INT_REG/USB_INT_REG) The USB cor

USB DEVICE S3C2440A RISC MICROPROCESSOR 13-8 Register Address R/W Description Reset ValueUSB_INT_REG 0x52000158(L) 0x5200

S3C2440A RISC MICROPROCESSOR USB DEVICE 13-9 INTERRUPT ENABLE REGISTER (EP_INT_EN_REG/USB_INT_EN_REG

USB DEVICE S3C2440A RISC MICROPROCESSOR 13-10 Register Address R/W Description Reset Value USB_INT_EN_REG 0x520016C(L) 0x

S3C2440A RISC MICROPROCESSOR USB DEVICE 13-11 FRAME NUMBER REGISTER (FPAME_NUM1_REG/FRAME_NUM2_REG)

S3C2440A RISC MICROPROCESSOR PRODUCT OVERVIEW 1-33 Table 1-4. S3C2440A Special Registers (Sheet 7 of 14) Register Name Address (B. Endian) Addr

USB DEVICE S3C2440A RISC MICROPROCESSOR 13-12 INDEX REGISTER (INDEX_REG) The INDEX register is used to indicate certain endp

S3C2440A RISC MICROPROCESSOR USB DEVICE 13-13 END POINT0 CONTROL STATUS REGISTER (EP0_CSR) This regi

USB DEVICE S3C2440A RISC MICROPROCESSOR 13-14 END POINT IN CONTROL STATUS REGISTER (IN_CSR1_REG/IN_CSR2_REG) Register Addre

S3C2440A RISC MICROPROCESSOR USB DEVICE 13-15 Register Address R/W Description Reset ValueIN_CSR2

USB DEVICE S3C2440A RISC MICROPROCESSOR 13-16 END POINT OUT CONTROL STATUS REGISTER (OUT_CSR1_REG/OUT_CSR2_REG) Register Add

S3C2440A RISC MICROPROCESSOR USB DEVICE 13-17 Register Address R/W Description Reset ValueOUT_CSR

USB DEVICE S3C2440A RISC MICROPROCESSOR 13-18 END POINT OUT WRITE COUNT REGISTER (OUT_FIFO_CNT1_REG/OUT_FIFO_CNT2_REG) These

S3C2440A RISC MICROPROCESSOR USB DEVICE 13-19 DMA INTERFACE CONTROL REGISTER (EPN_DMA_CON) Register

USB DEVICE S3C2440A RISC MICROPROCESSOR 13-20 DMA UNIT COUNTER REGISTER (EPN_DMA_UNIT) This register is valid in Demand mode

S3C2440A RISC MICROPROCESSOR USB DEVICE 13-21 DMA FIFO COUNTER REGISTER (EPN_DMA_FIFO) This register

PRODUCT OVERVIEW S3C2440A RISC MICROPROCESSOR 1-34 Table 1-4. S3C2440A Special Registers (Sheet 8 of 14) Register Name Address (B. Endian)Addres

USB DEVICE S3C2440A RISC MICROPROCESSOR 13-22 DMA TOTAL TRANSFER COUNTER REGISTER (EPn_DMA_TTC_L,M,H) This register should h

S3C2440A RISC MICROPROCESSOR INTERRUPT CONTROLLER 14-1 14 INTERRUPT CONTROLLER OVERVIEW The interrup

INTERRUPT CONTROLLER S3C2440A RISC MICROPROCESSOR 14-2 INTERRUPT CONTROLLER OPERATION F-bit and I-bit of Program Status Reg

S3C2440A RISC MICROPROCESSOR INTERRUPT CONTROLLER 14-3 INTERRUPT SOURCES The interrupt controller su

INTERRUPT CONTROLLER S3C2440A RISC MICROPROCESSOR 14-4 INTERRUPT SUB SOURCES Sub Sources Descriptions Source INT_AC97 AC

S3C2440A RISC MICROPROCESSOR INTERRUPT CONTROLLER 14-5 INTERRUPT PRIORITY GENERATING BLOCK The prior

INTERRUPT CONTROLLER S3C2440A RISC MICROPROCESSOR 14-6 INTERRUPT PRIORITY Each arbiter can handle six interrupt requests ba

S3C2440A RISC MICROPROCESSOR INTERRUPT CONTROLLER 14-7 INTERRUPT CONTROLLER SPECIAL REGISTERS There

INTERRUPT CONTROLLER S3C2440A RISC MICROPROCESSOR 14-8 SRCPND Bit Description Initial State INT_ADC [31] 0 = Not reque

S3C2440A RISC MICROPROCESSOR INTERRUPT CONTROLLER 14-9 . INTERRUPT MODE (INTMOD) REGISTER This reg

S3C2440A RISC MICROPROCESSOR PRODUCT OVERVIEW 1-35 Table 1-4. S3C2440A Special Registers (Sheet 9 of 14) Register Name Address (B. Endian) Addr

INTERRUPT CONTROLLER S3C2440A RISC MICROPROCESSOR 14-10 INTMOD Bit Description Initial State INT_ADC [31] 0 = IRQ,

S3C2440A RISC MICROPROCESSOR INTERRUPT CONTROLLER 14-11 INTERRUPT MASK (INTMSK) REGISTER This regist

INTERRUPT CONTROLLER S3C2440A RISC MICROPROCESSOR 14-12 INTMSK Bit Description Initial State INT_ADC [31] 0 = Service

S3C2440A RISC MICROPROCESSOR INTERRUPT CONTROLLER 14-13 PRIORITY REGISTER (PRIORITY) Register Addres

INTERRUPT CONTROLLER S3C2440A RISC MICROPROCESSOR 14-14 INTERRUPT PENDING (INTPND) REGISTER Each of the 32 bits in the inte

S3C2440A RISC MICROPROCESSOR INTERRUPT CONTROLLER 14-15 INTPND Bit Description Initial State INT_

INTERRUPT CONTROLLER S3C2440A RISC MICROPROCESSOR 14-16 INTERRUPT OFFSET (INTOFFSET) REGISTER The value in the interrupt of

S3C2440A RISC MICROPROCESSOR INTERRUPT CONTROLLER 14-17 SUB SOURCE PENDING (SUBSRCPND) REGISTER You

INTERRUPT CONTROLLER S3C2440A RISC MICROPROCESSOR 14-18 INTERRUPT SUB MASK (INTSUBMSK) REGISTER This register has 11 bits e

S3C2440A RISC MICROPROCESSOR LCD CONTROLLER 15-1 15 LCD CONTROLLER OVERVIEW The LCD controller in t

PRODUCT OVERVIEW S3C2440A RISC MICROPROCESSOR 1-36 Table 1-4. S3C2440A Special Registers (Sheet 10 of 14) Register Name Address (B. Endian) Add

LCD CONTROLLER S3C2440A RISC MICROPROCESSOR 15-2 COMMON FEATURES The LCD controller has a dedicated DMA that supports to

S3C2440A RISC MICROPROCESSOR LCD CONTROLLER 15-3 BLOCK DIAGRAM System BusLPC3600 is a timing contro

LCD CONTROLLER S3C2440A RISC MICROPROCESSOR 15-4 STN LCD CONTROLLER OPERATION TIMING GENERATOR (TIMEGEN) The TIMEGEN gen

S3C2440A RISC MICROPROCESSOR LCD CONTROLLER 15-5 Table 15-1. Relation between VCLK and CLKVAL (STN

LCD CONTROLLER S3C2440A RISC MICROPROCESSOR 15-6 256 Level Color Mode Operation The S3C2440A LCD controller can support

S3C2440A RISC MICROPROCESSOR LCD CONTROLLER 15-7 DITHERING AND FRAME RATE CONTROL In case of STN LC

LCD CONTROLLER S3C2440A RISC MICROPROCESSOR 15-8 Display Types The LCD controller supports 3 types of LCD drivers: 4-bit

S3C2440A RISC MICROPROCESSOR LCD CONTROLLER 15-9 MEMORY DATA FORMAT (STN, BSWP=0) Mono 4-bit Dual S

LCD CONTROLLER S3C2440A RISC MICROPROCESSOR 15-10 MEMORY DATA FORMAT ( STN, BSWP=0 ) (CONTINUED) In 4-level gray mode, 2

S3C2440A RISC MICROPROCESSOR LCD CONTROLLER 15-11 16 BPP Color mode 16 bits (5 bits of red, 6 bits

S3C2440A RISC MICROPROCESSOR PRODUCT OVERVIEW 1-37 Table 1-4. S3C2440A Special Registers (Sheet 11 of 14) Register Name Address (B. Endian) Add

LCD CONTROLLER S3C2440A RISC MICROPROCESSOR 15-12 4-bit Dual Scan Display4-bit Single Scan Display8-bit Single Scan Displ

S3C2440A RISC MICROPROCESSOR LCD CONTROLLER 15-13 VD3R1VD2G1VD1B1VD0R2VD3G2VD2B2VD1R3VD0G3...1 P

LCD CONTROLLER S3C2440A RISC MICROPROCESSOR 15-14 Timing Requirements Image data should be transferred from the memory to

S3C2440A RISC MICROPROCESSOR LCD CONTROLLER 15-15 WDLYWLHLINE1LINE2LINE3LINE4LINE5LINE6 LINE1LINEnF

LCD CONTROLLER S3C2440A RISC MICROPROCESSOR 15-16 TFT LCD CONTROLLER OPERATION The TIMEGEN generates the control signals

S3C2440A RISC MICROPROCESSOR LCD CONTROLLER 15-17 MEMORY DATA FORMAT (TFT) This section includes s

LCD CONTROLLER S3C2440A RISC MICROPROCESSOR 15-18 16BPP Display (BSWP = 0, HWSWP = 0) D[31:16] D[15:0] 000H P1 P2 004H

S3C2440A RISC MICROPROCESSOR LCD CONTROLLER 15-19 8BPP Display (BSWP = 0, HWSWP = 0) D[31:24] D[2

LCD CONTROLLER S3C2440A RISC MICROPROCESSOR 15-20 4BPP Display (BSWP = 0, HWSWP = 0) D[31:28] D[27:24] D[23:20] D[19:1

S3C2440A RISC MICROPROCESSOR LCD CONTROLLER 15-21 256 PALETTE USAGE (TFT) Palette Configuration and

PRODUCT OVERVIEW S3C2440A RISC MICROPROCESSOR 1-38 Table 1-4. S3C2440A Special Registers (Sheet 12 of 14) Register Name Address (B. Endian) Add

LCD CONTROLLER S3C2440A RISC MICROPROCESSOR 15-22 1 2 3 4 5LCD Panel16BPP 5:5:5+1 Format(Non-Palette)A[31] A[30] A[29]

S3C2440A RISC MICROPROCESSOR LCD CONTROLLER 15-23 INT_FrSynVSYNCHSYNCVDENHSYNCVCLKVDLENDVBPD+1VSPW+

LCD CONTROLLER S3C2440A RISC MICROPROCESSOR 15-24 SAMSUNG TFT LCD PANEL (3.5” PORTRAIT / 256K COLOR / REFLECTIVE A-SI/TRA

S3C2440A RISC MICROPROCESSOR LCD CONTROLLER 15-25 VIRTUAL DISPLAY (TFT/STN) The S3C2440A supports h

LCD CONTROLLER S3C2440A RISC MICROPROCESSOR 15-26 LCD POWER ENABLE (STN/TFT) The S3C2440A provides Power enable (PWREN) f

S3C2440A RISC MICROPROCESSOR LCD CONTROLLER 15-27 LCD CONTROLLER SPECIAL REGISTERS LCD Control 1 Re

LCD CONTROLLER S3C2440A RISC MICROPROCESSOR 15-28 LCD Control 2 Register Register Address R/W Description Reset ValueLC

S3C2440A RISC MICROPROCESSOR LCD CONTROLLER 15-29 LCD Control 3 Register Register Address R/W Desc

LCD CONTROLLER S3C2440A RISC MICROPROCESSOR 15-30 LCD Control 4 Register Register Address R/W Description Reset ValueLC

S3C2440A RISC MICROPROCESSOR LCD CONTROLLER 15-31 LCD Control 5 Register Register Address R/W Desc

S3C2440A RISC MICROPROCESSOR PRODUCT OVERVIEW 1-3 FEATURES (Continued) Interrupt Controller • 60 Interrupt sources (One Watch dog timer, 5 time

S3C2440A RISC MICROPROCESSOR PRODUCT OVERVIEW 1-39 Table 1-4. S3C2440A Special Registers (Sheet 13 of 14) Register Name Address (B. Endian) Add

LCD CONTROLLER S3C2440A RISC MICROPROCESSOR 15-32 LCD Control 5 Register (Continued) LCDCON5 Bit Description Initial st

S3C2440A RISC MICROPROCESSOR LCD CONTROLLER 15-33 FRAME BUFFER START ADDRESS 1 REGISTER Register Ad

LCD CONTROLLER S3C2440A RISC MICROPROCESSOR 15-34 FRAME Buffer Start Address 3 Register Register Address R/W Description

S3C2440A RISC MICROPROCESSOR LCD CONTROLLER 15-35 RED Lookup Table Register Register Address R/W D

LCD CONTROLLER S3C2440A RISC MICROPROCESSOR 15-36 Dithering Mode Register Register Address R/W Description Reset Valu

S3C2440A RISC MICROPROCESSOR LCD CONTROLLER 15-37 Temp Palette Register Register Address R/W Des

LCD CONTROLLER S3C2440A RISC MICROPROCESSOR 15-38 LCD Interrupt Pending Register Register Address R/W Description Res

S3C2440A RISC MICROPROCESSOR LCD CONTROLLER 15-39 LCD Interrupt Mask Register Register Address R/

LCD CONTROLLER S3C2440A RISC MICROPROCESSOR 15-40 TCON Control Register Register Address R/W Description Reset Value

S3C2440A RISC MICROPROCESSOR LCD CONTROLLER 15-41 Register Setting Guide (STN) The LCD controller s

PRODUCT OVERVIEW S3C2440A RISC MICROPROCESSOR 1-40 Table 1-4. S3C2440A Special Registers (Sheet 14 of 14) Register Name Address (B. Endian) Add

LCD CONTROLLER S3C2440A RISC MICROPROCESSOR 15-42 Example 1: 160 x 160, 4-level gray, 80 frame/sec, 4-bit single scan di

S3C2440A RISC MICROPROCESSOR LCD CONTROLLER 15-43 Gray Level Selection Guide The S3C2440A LCD contr

LCD CONTROLLER S3C2440A RISC MICROPROCESSOR 15-44 Register Setting Guide (TFT LCD) The CLKVAL register value determines t

S3C2440A RISC MICROPROCESSOR ADC AND TOUCH SCREEN INTERFACE 16-1 16 ADC & TOUCH SCREEN INTERFACE OVERVIEW The 10-bit CMOS ADC (Analog to Di

ADC AND TOUCH SCREEN INTERFACE S3C2440A RISC MICROPROCESSOR 16-2 ADC & TOUCH SCREEN INTERFACE OPERATION BLOCK DIAGRAM Figure 16-1 shows the

S3C2440A RISC MICROPROCESSOR ADC AND TOUCH SCREEN INTERFACE 16-3 FUNCTION DESCRIPTIONS A/D Conversion Time When the GCLK frequency is 50MHz and

ADC AND TOUCH SCREEN INTERFACE S3C2440A RISC MICROPROCESSOR 16-4 Programming Notes 1. The A/D converted data can be accessed by means of i

S3C2440A RISC MICROPROCESSOR ADC AND TOUCH SCREEN INTERFACE 16-5 ADC AND TOUCH SCREEN INTERFACE SPECIAL REGISTERS ADC CONTROL REGISTER (ADCCON)

ADC AND TOUCH SCREEN INTERFACE S3C2440A RISC MICROPROCESSOR 16-6 ADC TOUCH SCREEN CONTROL REGISTER (ADCTSC) Register Address R/W Description

S3C2440A RISC MICROPROCESSOR ADC AND TOUCH SCREEN INTERFACE 16-7 ADC START DELAY REGISTER (ADCDLY) Register Address R/W Description Reset Va

S3C2440A RISC MICROPROCESSOR PROGRAMMER'S MODEL 2-1 2 PROGRAMMER'S MODEL OVERVIEW S3C2440A is developed using the advanced ARM920T cor

ADC AND TOUCH SCREEN INTERFACE S3C2440A RISC MICROPROCESSOR 16-8 ADC CONVERSION DATA REGISTER (ADCDAT0) Register Address R/W Description Rese

S3C2440A RISC MICROPROCESSOR ADC AND TOUCH SCREEN INTERFACE 16-9 ADC CONVERSION DATA REGISTER (ADCDAT1) Register Address R/W Description Rese

ADC AND TOUCH SCREEN INTERFACE S3C2440A RISC MICROPROCESSOR 16-10 NOTES

S3C2440A RISC MICROPROCESSOR REAL TIME CLOCK 17-1 17 REAL TIME CLOCK OVERVIEW The Real Time Cloc

REAL TIME CLOCK S3C2440A RISC MICROPROCESSOR 17-2 REAL TIME CLOCK OPERATION 215 Clock DividerXTOrtcXTIrtcControl RegisterSE

S3C2440A RISC MICROPROCESSOR REAL TIME CLOCK 17-3 ALARM FUNCTION The RTC generates an alarm signal

REAL TIME CLOCK S3C2440A RISC MICROPROCESSOR 17-4 REAL TIME CLOCK SPECIAL REGISTERS REAL TIME CLOCK CONTROL (RTCCON) REGIST

S3C2440A RISC MICROPROCESSOR REAL TIME CLOCK 17-5 RTC ALARM CONTROL (RTCALM) REGISTER The RTCALM

REAL TIME CLOCK S3C2440A RISC MICROPROCESSOR 17-6 ALARM SECOND DATA (ALMSEC) REGISTER Register Address R/W Description R

S3C2440A RISC MICROPROCESSOR REAL TIME CLOCK 17-7 ALARM DATE DATA (ALMDATE) REGISTER Register Add

PROGRAMMER'S MODEL S3C2440A RISC MICROPROCESSOR 2-2 BIG-ENDIAN FORMAT In Big-Endian format, the most significant byte of a word is stored

REAL TIME CLOCK S3C2440A RISC MICROPROCESSOR 17-8 BCD SECOND (BCDSEC) REGISTER Register Address R/W Description Reset Va

S3C2440A RISC MICROPROCESSOR REAL TIME CLOCK 17-9 BCD DATE (BCDDATE) REGISTER Register Address R

REAL TIME CLOCK S3C2440A RISC MICROPROCESSOR 17-10 BCD YEAR (BCDYEAR) REGISTER Register Address R/W Description Reset Va

S3C2440A RISC MICROPROCESSOR WATCHDOG TIMER 18-1 18 WATCHDOG TIMER OVERVIEW The S3C2440A watchdog

WATCHDOG TIMER S3C2440A RISC MICROPROCESSOR 18-2 WATCHDOG TIMER OPERATION Figure 18-1 shows the functional block diagram of the watchdog timer

S3C2440A RISC MICROPROCESSOR WATCHDOG TIMER 18-3 WATCHDOG TIMER SPECIAL REGISTERS WATCHDOG TIMER CO

WATCHDOG TIMER S3C2440A RISC MICROPROCESSOR 18-4 WATCHDOG TIMER DATA (WTDAT) REGISTER The WTDAT register is used to specify the time-out dura

S3C2440A RISC MICROPROCESSOR MMC/SD/SDIO CONTROLLER 19-1 19 MMC/SD/SDIO Controller FEATURES  SD M

MMC/SD/SDIO CONTROLLER S3C2440A RISC MICROPROCESSOR 19-2 SD OPERATION A serial clock line synchronizes shifting and sampling of the information

S3C2440A RISC MICROPROCESSOR MMC/SD/SDIO CONTROLLER 19-3 SDIO OPERATION There are two functions of SDIO operation: SDIO Interrupt receiving and

S3C2440A RISC MICROPROCESSOR PROGRAMMER'S MODEL 2-3 OPERATING MODES ARM920T supports seven modes of operation: • User (usr): The normal ARM

MMC/SD/SDIO CONTROLLER S3C2440A RISC MICROPROCESSOR 19-4 SDI SPECIAL REGISTERS SDI Control Register(SDICON) Register Address R/W Description

S3C2440A RISC MICROPROCESSOR MMC/SD/SDIO CONTROLLER 19-5 SDI Command Argument Register(SDICmdArg) Register Address R/W Description Reset Valu

MMC/SD/SDIO CONTROLLER S3C2440A RISC MICROPROCESSOR 19-6 SDI Command Status Register(SDICmdSta) Register Address R/W Description Reset Value

S3C2440A RISC MICROPROCESSOR MMC/SD/SDIO CONTROLLER 19-7 SDI Response Register 2(SDIRSP2) Register Address R/W Description Reset Value SDIRSP

MMC/SD/SDIO CONTROLLER S3C2440A RISC MICROPROCESSOR 19-8 SDI Data Control Register(SDIDatCon) Register Address R/W Description Reset Value S

S3C2440A RISC MICROPROCESSOR MMC/SD/SDIO CONTROLLER 19-9 SDI Data Remain Counter Register(SDIDatCnt) Register Address R/W Description Reset Va

MMC/SD/SDIO CONTROLLER S3C2440A RISC MICROPROCESSOR 19-10 SDI FIFO Status Register(SDIFSTA) Register Address R/W Description Reset Value SDIF

S3C2440A RISC MICROPROCESSOR MMC/SD/SDIO CONTROLLER 19-11 SDI Interrupt Mask Register(SDIIntMsk) Register Address R/W Description Reset Value

MMC/SD/SDIO CONTROLLER S3C2440A RISC MICROPROCESSOR 19-12 SDI Data Register(SDIDAT) Register Address R/W Description Reset Value SDIDAT 0x5A0

S3C2440A RISC MICROPROCESSOR IIC-BUS I

PROGRAMMER'S MODEL S3C2440A RISC MICROPROCESSOR 2-4 R0R1R2R3R4R5R6R7R9R8R10R11R12R13R14R15 (PC)R0R1R2R3R4R5R6R7R9R8R10R11R12R13_svcR14_svc

IIC-BUS INTERFACE S3C2440A RISC MICROPROCESSOR 20-2 PCLKAddress RegisterSDA4-bit PrescalerIIC-Bus Control LogicIICSTATIICCONComparatorShift Registe

S3C2440A RISC MICROPROCESSOR IIC-BUS I

IIC-BUS INTERFACE S3C2440A RISC MICROPROCESSOR 20-4 DATA TRANSFER FORMAT Every byte placed on the SDA line should be eight bits in length. The byte

S3C2440A RISC MICROPROCESSOR IIC-BUS I

IIC-BUS INTERFACE S3C2440A RISC MICROPROCESSOR 20-6 READ-WRITE OPERATION In Transmitter mode, when the data is transferred, the IIC-bus interface w

S3C2440A RISC MICROPROCESSOR IIC-BUS I

IIC-BUS INTERFACE S3C2440A RISC MICROPROCESSOR 20-8 Write slave address toIICDS.Write 0xB0 (M/R Start)to IICSTAT.The data of the IICDS (slaveaddre

S3C2440A RISC MICROPROCESSOR IIC-BUS I

IIC-BUS INTERFACE S3C2440A RISC MICROPROCESSOR 20-10 IIC detects start signal. and, IICDSreceives data.IIC compares IICADD and IICDS (thereceived

S3C2440A RISC MICROPROCESSOR IIC-BUS I

S3C2440A RISC MICROPROCESSOR PROGRAMMER'S MODEL 2-5 The THUMB State Register Set The THUMB state register set is a subset of the ARM state s

IIC-BUS INTERFACE S3C2440A RISC MICROPROCESSOR 20-12 MULTI-MASTER IIC-BUS CONTROL/STATUS (IICSTAT) REGISTER Register Address R/W Description Rese

S3C2440A RISC MICROPROCESSOR IIC-BUS I

IIC-BUS INTERFACE S3C2440A RISC MICROPROCESSOR 20-14 MULTI-MASTER IIC-BUS LINE CONTROL(IICLC) REGISTER Register Address R/W Description Reset Val

S3C2440A RISC MICROPROCESSOR IIS-BUS INTERFACE 21-1 21 IIS-BUS INTERFACE OVERVIEW Currently, many d

IIS-BUS INTERFACE S3C2440A RISC MICROPROCESSOR 21-2 BLOCK DIAGRAM ADDRDATACNTLPCLKBRFCIPSR_AIPSR_BTxFIFORxFIFOSCLKGCHNCSFTR

S3C2440A RISC MICROPROCESSOR IIS-BUS INTERFACE 21-3 DMA TRANSFER In this mode, transmit or receive FI

IIS-BUS INTERFACE S3C2440A RISC MICROPROCESSOR 21-4 IIS-bus Format (N=8 or 16)MSB(1st)2ndBitN-1thBitLSB(last)MSB(1st)2ndBit

S3C2440A RISC MICROPROCESSOR IIS-BUS INTERFACE 21-5 IIS-BUS INTERFACE SPECIAL REGISTERS IIS CONTROL (

IIS-BUS INTERFACE S3C2440A RISC MICROPROCESSOR 21-6 IIS MODE REGISTER (IISMOD) REGISTER Register Address R/W Description Re

S3C2440A RISC MICROPROCESSOR IIS-BUS INTERFACE 21-7 IIS PRESCALER (IISPSR) REGISTER Register Address

PROGRAMMER'S MODEL S3C2440A RISC MICROPROCESSOR 2-6 The relationship between ARM and THUMB state registers The relationship between ARM a

IIS-BUS INTERFACE S3C2440A RISC MICROPROCESSOR 21-8 IIS FIFO CONTROL (IISFCON) REGISTER Register Address R/W Description Re

S3C2440A RISC MICROPROCESSOR SPI 22-1 22 SPI OVERVIEW The S3C2440A Serial Peripheral Interface (SPI) can interface with the serial data t

SPI S3C2440A RISC MICROPROCESSOR 22-2 BLOCK DIAGRAM 8bit Prescaler 1PCLKStatus Register 1Prescaler Register 1/SSnSS 0SCKSPIC

S3C2440A RISC MICROPROCESSOR SPI 22-3 SPI OPERATION Using the SPI interface, S3C2440A can send/receive 8-bit data simultaneously with an extern

SPI S3C2440A RISC MICROPROCESSOR 22-4 SPI TRANSFER FORMAT The S3C2440A supports 4 different formats to transfer data. Figure

S3C2440A RISC MICROPROCESSOR SPI 22-5 TRANSMITTING PROCEDURE FOR DMA 1. SPI is configured as DMA mode. 2. DMA is configured properly. 3. SPI

SPI S3C2440A RISC MICROPROCESSOR 22-6 SPI SPECIAL REGISTERS SPI CONTROL REGISTER Register Address R/W Description Reset Val

S3C2440A RISC MICROPROCESSOR SPI 22-7 SPI STATUS REGISTER Register Address R/W Description Reset Value SPSTA0 0x59000004 R SPI channel 0 s

SPI S3C2440A RISC MICROPROCESSOR 22-8 The SPIMISO (MISO) and SPIMOSI (MOSI) data pins are used for transmitting and receiving

S3C2440A RISC MICROPROCESSOR CAMERA INTERFACE 23-1 23 CAMERA INTERFACE OVERVIEW This chapter will explain the specification and defines the cam

S3C2440A RISC MICROPROCESSOR PROGRAMMER'S MODEL 2-7 Accessing Hi-Registers in THUMB State In THUMB state, registers R8-R15 (“Hi registers”)

S3C2440A RISC MICROPROCESSOR CAMERA INTERFACE 23-2

S3C2440A RISC MICROPROCESSOR CAMERA INTERFACE 23-3 TIMING DIAGRAM jht}zujjht}zujjht}zujjht}zuj j  j  j  j  jjhtoylmjhtoylmjhtoylmj

S3C2440A RISC MICROPROCESSOR CAMERA INTERFACE 23-4

S3C2440A RISC MICROPROCESSOR CAMERA INTERFACE 23-5 CAMERA INTERFACE OPERATION TWO DMA PATHS CAMIF has 2 DMA paths. P-path (Preview path) and C-p

S3C2440A RISC MICROPROCESSOR CAMERA INTERFACE 23-6

S3C2440A RISC MICROPROCESSOR CAMERA INTERFACE 23-7 MEMORY STORING METHOD The little-endian method in codec path is used to store in the frame me

S3C2440A RISC MICROPROCESSOR CAMERA INTERFACE 23-8

S3C2440A RISC MICROPROCESSOR CAMERA INTERFACE 23-9 TIMING DIAGRAM FOR LAST IRQ IRQ except LastIRQ is generated before image capturing. Last IRQ

S3C2440A RISC MICROPROCESSOR CAMERA INTERFACE 23-10

S3C2440A RISC MICROPROCESSOR CAMERA INTERFACE 23-11 WINDOW OPTION REGISTER Register Address R/W Description Reset Value CIWDOFST 0x4F000004

PROGRAMMER'S MODEL S3C2440A RISC MICROPROCESSOR 2-8 The Condition Code Flags The N, Z, C and V bits are the condition code flags. These ma

S3C2440A RISC MICROPROCESSOR CAMERA INTERFACE 23-12

S3C2440A RISC MICROPROCESSOR CAMERA INTERFACE 23-13 Y3 START ADDRESS REGISTER Register Address R/W Description Reset Value CICOYSA3 0x4F00002

S3C2440A RISC MICROPROCESSOR CAMERA INTERFACE 23-14

S3C2440A RISC MICROPROCESSOR CAMERA INTERFACE 23-15 CODEC TARGET FORMAT REGISTER Register Address R/W Description Reset Value CICOTRGFMT 0x4

S3C2440A RISC MICROPROCESSOR CAMERA INTERFACE 23-16

S3C2440A RISC MICROPROCESSOR CAMERA INTERFACE 23-17 REGISTER SETTING GUIDE FOR CODEC SCALER AND PREVIEW SCALER SRC_Width and DST_Width satisfy t

S3C2440A RISC MICROPROCESSOR CAMERA INTERFACE 23-18

S3C2440A RISC MICROPROCESSOR CAMERA INTERFACE 23-19 CODEC MAIN-SCALER CONTROL REGISTER Register Address R/W Description Reset Value CICOSCCTR

S3C2440A RISC MICROPROCESSOR CAMERA INTERFACE 23-20

S3C2440A RISC MICROPROCESSOR CAMERA INTERFACE 23-21 RGB3 START ADDRESS REGISTER Register Address R/W Description Reset Value CIPRCLRSA3 0x4F0

PRODUCT OVERVIEW S3C2440A RISC MICROPROCESSOR 1-4 FEATURES (Continued) A/D Converter & Touch Screen Interface • 8-ch multiplexed ADC • Max

S3C2440A RISC MICROPROCESSOR PROGRAMMER'S MODEL 2-9 Table 2-1. PSR Mode Bit Values M[4:0] Mode Visible THUMB state registers Visible ARM

S3C2440A RISC MICROPROCESSOR CAMERA INTERFACE 23-22

S3C2440A RISC MICROPROCESSOR CAMERA INTERFACE 23-23 PREVIEW PRE-SCALER CONTROL REGISTER 2 Register Address R/W Description Reset Value CIPRSCP

S3C2440A RISC MICROPROCESSOR CAMERA INTERFACE 23-24

S3C2440A RISC MICROPROCESSOR AC97 CONT

AC97 CONTROLLER S3C2440A RISC MICROPROCESSOR 24-2 AC97 CONTROLLER OPERATION BLOCK DIAGRAM Figure 24-1 shows the functional block diagram of the S3C

S3C2440A RISC MICROPROCESSOR AC97 CONT

AC97 CONTROLLER S3C2440A RISC MICROPROCESSOR 24-4 OPERATION FLOW CHART System reset or Cold resetSet GPIO and ReleaseINTMSK/SUBINTMSK bitsEnable Co

S3C2440A RISC MICROPROCESSOR AC97 CONT

AC97 CONTROLLER S3C2440A RISC MICROPROCESSOR 24-6 AC-LINK INPUT FRAME (SDATA_IN) SDATA_OUTBIT_CLKSYNCAC '97 samples SYNC assertion hereAC &apo

S3C2440A RISC MICROPROCESSOR AC97 CONT

PROGRAMMER'S MODEL S3C2440A RISC MICROPROCESSOR 2-10 EXCEPTIONS Exceptions arise whenever the normal flow of a program has to be halted te

AC97 CONTROLLER S3C2440A RISC MICROPROCESSOR 24-8 AC97 CONTROLLER SPECIAL REGISTERS AC97 GLOBAL CONTROL REGISTER (AC_GLBCTRL) Register Address R/W

S3C2440A RISC MICROPROCESSOR AC97 CONT

AC97 CONTROLLER S3C2440A RISC MICROPROCESSOR 24-10 AC97 CODEC STATUS REGISTER (AC_CODEC_STAT) Register Address R/W Description Reset ValueAC_CODE

S3C2440A RISC MICROPROCESSOR AC97 CONT

AC97 CONTROLLER S3C2440A RISC MICROPROCESSOR 24-12 NOTES

S3C2440A RISC MICROPROCESSOR BUS PRIORITIES 25-1 25 BUS PRIORITIES OVERVIEW The bus arbitration log

BUS PRIORITIES S3C2440A RISC MICROPROCESSOR 25-2 NOTES

S3C2440A RISC MICROPROCESSOR MECHANICAL DATA 26-1 26 MECHANICAL DATA PACKAGE DIMENSIONS 14.0014.000.35 + 0.051.2

MECHANICAL DATA S3C2440A RISC MICROPROCESSOR 26-2 A1 INDEX MARK0.80 x 16 = 12.80 ± 0.0514.000.800.80ABCDEFGHJKLMNPRTU891011121314151617 567123414.

S3C2440A RISC MICROPROCESSOR ELECTRICAL DATA 27-1 27 ELECTRICAL DATA ABSOLUTE MAXIMUM RATINGS Table 27-1 Absolute Maximum Rating Parameter S

S3C2440A RISC MICROPROCESSOR PROGRAMMER'S MODEL 2-11 Exception Entry/Exit Summary Table 2-2 summarizes the PC value preserved in the relevan

ELECTRICAL DATA S3C2440A RISC MICROPROCESSOR 27-2 RECOMMENDED OPERATING CONDITIONS Table 27-2 Recommended Operating Conditions

S3C2440A RISC MICROPROCESSOR ELECTRICAL DATA 27-3 D.C. ELECTRICAL CHARACTERISTICS Table 27-3 and 27-4 defines the DC electrical characteristic

ELECTRICAL DATA S3C2440A RISC MICROPROCESSOR 27-4 Normal I/O PAD DC Electrical Characteristics for Memory (VDDMOP=3.0V±±±±0.3V

S3C2440A RISC MICROPROCESSOR ELECTRICAL DATA 27-5 Normal I/O PAD DC Electrical Characteristics for I/O (VDDOP = 3.3V ±±±± 0.3V, TA = -40 to 85

ELECTRICAL DATA S3C2440A RISC MICROPROCESSOR 27-6 Table 27-4 USB DC Electrical Characteristics Symbol Parameter Condition Mi

S3C2440A RISC MICROPROCESSOR ELECTRICAL DATA 27-7 400Mhz Power consumption88mW87mW139mW68mW050100150200250DVS(o) DVS(x)ItemPower[mW]Core Power

ELECTRICAL DATA S3C2440A RISC MICROPROCESSOR 27-8

S3C2440A RISC MICROPROCESSOR ELECTRICAL DATA 27-9 A.C. ELECTRICAL CHARACTERISTICS 1/2 VDD1/2 VDDtXTALCYCNOTE:Clock input is from the XTIpll pi

ELECTRICAL DATA S3C2440A RISC MICROPROCESSOR 27-10 HCLK(internal)SCLKCLKOUT(HCLK)tHC2CKtHC2SCLK Figure 27-5 HCLK/CLKOUT/SCLK i

S3C2440A RISC MICROPROCESSOR ELECTRICAL DATA 27-11 nRESETXTIpll orEXTCLKVCOoutputMCU operates by XTIpll or EXTCLK clcok.ClockDisabletPLLFCLK i

PROGRAMMER'S MODEL S3C2440A RISC MICROPROCESSOR 2-12 IRQ The IRQ (Interrupt Request) exception is a normal interrupt caused by a LOW level

ELECTRICAL DATA S3C2440A RISC MICROPROCESSOR 27-12 XTIpllVCOOutputClockDisableFCLKSeveral slow clocks (XTIpll or EXTCLK)Power

S3C2440A RISC MICROPROCESSOR ELECTRICAL DATA 27-13 HCLKnGCSxtRADnOEDATAADDRnBExtRCDtRODtRODtRCDTacctRAD tRAD tRAD tRAD tRAD tRAD tRAD tRADtRDS

ELECTRICAL DATA S3C2440A RISC MICROPROCESSOR 27-14 HCLKnGCSxtRADnOEDATAADDRnBExtRCDtRODtRODtRCDtRBED tRBEDTacctRAD tRAD tRAD t

S3C2440A RISC MICROPROCESSOR ELECTRICAL DATA 27-15 HCLKnGSnOEADDRtXnBRQSXnBREQtXnBRQHXnBACK'HZ''HZ''HZ'tXnBACKDt

ELECTRICAL DATA S3C2440A RISC MICROPROCESSOR 27-16 HCLKnGCSxtRADTacsnOETcosDATAADDRnWBEx '1'TochTcahtRCDtRODtRDStRDH

S3C2440A RISC MICROPROCESSOR ELECTRICAL DATA 27-17 HCLKnGCSxtRADTacsnOETcosDATAADDRnBExTochTcahtRCDtRODtRDStRDHtRODtRCDtRADtRBEDtRBEDTacc Figu

ELECTRICAL DATA S3C2440A RISC MICROPROCESSOR 27-18 HCLKnGCSxtRADTacsnWETcosDATAADDRnWBExTochTcahtRCDtRWDtRDDtRWDtRCDtRADTcosTo

S3C2440A RISC MICROPROCESSOR ELECTRICAL DATA 27-19 HCLKnGCSxtRADTacsnWETcosDATAADDRnBExTochTcahtRCDtRWDtRDDtRWDtRCDtRADtRBED tRBEDTacctRDD Fig

ELECTRICAL DATA S3C2440A RISC MICROPROCESSOR 27-20 HCLKnGCSxnOETacc = 6cyclenWaitDATAADDRTacsTacsdelayedtRCNOTE: The status o

S3C2440A RISC MICROPROCESSOR ELECTRICAL DATA 27-21 HCLKnGCSxtRADTacsnOETcosDATAADDRtRCDtRODtRDStRDHtRADTacc Figure 27-18 Masked-ROM Single REA

S3C2440A RISC MICROPROCESSOR PROGRAMMER'S MODEL 2-13 Software Interrupt The Software Interrupt Instruction (SWI) is used for entering Super

ELECTRICAL DATA S3C2440A RISC MICROPROCESSOR 27-22 SCLKnSRAStSADTrpnSCASDATAADDR/BAnBExtSRDtSDStSDHSCKEA10/APnGCSxtSCSDnWEtSAD

S3C2440A RISC MICROPROCESSOR ELECTRICAL DATA 27-23 SCLKnSRASnSCASADDR/BAnBExtXnBRQHtXnBRQSSCKEA10/APnGCSxnWE'1'XnBREQXnBACKEXTCLKtXn

ELECTRICAL DATA S3C2440A RISC MICROPROCESSOR 27-24 SCLKnSRAStSADnSCASDATAADDR/BAnBExtSRDSCKEA10/APnGCSxtSCSDnWEtSADtSCDtSWD&ap

S3C2440A RISC MICROPROCESSOR ELECTRICAL DATA 27-25 SCLKnSRAStSADTrpnSCASDATAADDR/BAnBExtSRDtSDStSDHSCKEA10/APnGCSxtSCSDnWEtSADtSCDtSWD'1&

ELECTRICAL DATA S3C2440A RISC MICROPROCESSOR 27-26 SCLKnSRAStSADTrpnSCASDATAADDR/BAnBExtSRDtSDStSDHSCKEA10/APnGCSxtSCSDnWEtSAD

S3C2440A RISC MICROPROCESSOR ELECTRICAL DATA 27-27 SCLKnSRAStSADTrpnSCASDATAADDR/BAnBExtSRDSCKEA10/APnGCSxtSCSDnWEtSADtSCDtSWD'1'tSA

ELECTRICAL DATA S3C2440A RISC MICROPROCESSOR 27-28 SCLKnSRAStSADTrpnSCASDATAADDR/BAnBExtSRDtSDStSDHSCKEA10/APnGCSxtSCSDnWEtSAD

S3C2440A RISC MICROPROCESSOR ELECTRICAL DATA 27-29 SCLKnSRAStSADTrpnSCASDATAADDR/BAnBExtSRDSCKEA10/APnGCSxtSCSDnWEtSADtSCDtSWDtSADtSCSDtSRD&ap

ELECTRICAL DATA S3C2440A RISC MICROPROCESSOR 27-30 SCLKnSRAStSADTrpnSCASDATAADDR/BAnBExtSRDtSDDtSDDSCKEA10/APnGCSxtSCSDnWEtSAD

S3C2440A RISC MICROPROCESSOR ELECTRICAL DATA 27-31 SCLKnSRAStSADTrpnSCASDATAADDR/BAnBExtSRDtSDDtSDDSCKEA10/APnGCSxtSCSDnWEtSADtSCDtSWD'1&

PROGRAMMER'S MODEL S3C2440A RISC MICROPROCESSOR 2-14 Exception Priorities When multiple exceptions arise at the same time, a fixed priorit

ELECTRICAL DATA S3C2440A RISC MICROPROCESSOR 27-32 XSCLKtXRStXRStCADLtCADHtXADXnXDREQXnXDACKRead WriteMin. 3SCLK Figure 27-30.

S3C2440A RISC MICROPROCESSOR ELECTRICAL DATA 27-33 IISSCLKtLRCKIISLRCK (out)tSDOIISLRCK (out)tSDIHtSDISIISSDI (in) Figure 27-32. IIS Interface

ELECTRICAL DATA S3C2440A RISC MICROPROCESSOR 27-34 SDCLKtSDCDSDCMD (out)tSDCHtSDCStSDDDSDCMD (in)tSDDHtSDDSSDDATA[3:0] (in)SDD

S3C2440A RISC MICROPROCESSOR ELECTRICAL DATA 27-35 TACLS TWRPH0 TWRPH1COMMANDTWRPH0 TWRPH1ADDRESSHCLKALEnFWEDATA[7:0] DATA[7:0]HCLKCLEnFWEtCLE

ELECTRICAL DATA S3C2440A RISC MICROPROCESSOR 27-36 Table 27-7 Clock Timing Constants (VDDi, VDDalive, VDDiarm = 1.2 V ± 0.1 V,

S3C2440A RISC MICROPROCESSOR ELECTRICAL DATA 27-37 Table 27-8 ROM/SRAM Bus Timing Constants (VDDi, VDDalive, VDDiarm = 1.2 V ± 0.1 V, TA = -40

ELECTRICAL DATA S3C2440A RISC MICROPROCESSOR 27-38 Table 27-10 External Bus Request Timing Constants (VDD = 1.2 V ± 0.1 V, TA

S3C2440A RISC MICROPROCESSOR ELECTRICAL DATA 27-39 Table 27-12 TFT LCD Controller Module Signal Timing Constants (VDD = 1.2 V ± 0.05 V, TA = -

ELECTRICAL DATA S3C2440A RISC MICROPROCESSOR 27-40 Table 27-14 IIC BUS Controller Module Signal Timing (VDD = 1.2 V ± 0.05 V,

S3C2440A RISC MICROPROCESSOR ELECTRICAL DATA 27-41 Table 27-16 SPI Interface Transmit/Receive Timing Constants (VDD = 1.2 V ± 0.1 V, TA = -40

S3C2440A RISC MICROPROCESSOR PROGRAMMER'S MODEL 2-15 INTERRUPT LATENCIES The worst case latency for FIQ, assuming that it is enabled, consis

ELECTRICAL DATA S3C2440A RISC MICROPROCESSOR 27-42 Table 27-18 USB Full Speed Output Buffer Electrical Characteristics (VDD =

PROGRAMMER'S MODEL S3C2440A RISC MICROPROCESSOR 2-16 NOTES

S3C2440A RISC MICROPROCESSOR ARM INSTRUCTION SET 3-1 3 ARM INSTRUCTION SET INSTRUCTION SET SUMMAY This chapter describes the ARM instruction se

ARM INSTRUCTION SET S3C2440A RISC MICROPROCESSOR 3-2 NOTES Some instruction codes are not defined but does not cause Undefined instruction trap

S3C2440A RISC MICROPROCESSOR PRODUCT OVERVIEW 1-5 BLOCK DIAGRAM ARM920TARM9TDMIProcessor core(Internal Embedded ICE)DD[31:0]WriteBackPA TagRAMDa

S3C2440A RISC MICROPROCESSOR ARM INSTRUCTION SET 3-3 Table 3-1. The ARM Instruction Set (Continued) Mnemonic Instruction Action MRC Move from

ARM INSTRUCTION SET S3C2440A RISC MICROPROCESSOR 3-4 THE CONDITION FIELD In ARM state, all instructions are conditionally executed according to

S3C2440A RISC MICROPROCESSOR ARM INSTRUCTION SET 3-5 BRANCH AND EXCHANGE (BX) This instruction is only executed if the condition is true. The va

ARM INSTRUCTION SET S3C2440A RISC MICROPROCESSOR 3-6 Examples ADR R0, Into_THUMB + 1 Generate branch target address and set bit 0 high – hen

S3C2440A RISC MICROPROCESSOR ARM INSTRUCTION SET 3-7 BRANCH AND BRANCH WITH LINK (B, BL) The instruction is only executed if the condition is tr

ARM INSTRUCTION SET S3C2440A RISC MICROPROCESSOR 3-8 ASSEMBLER SYNTAX Items in “{}” are optional. Items in “<>” must be present. B{L}{cond

S3C2440A RISC MICROPROCESSOR ARM INSTRUCTION SET 3-9 DATA PROCESSING The data processing instruction is only executed if the condition is true.

ARM INSTRUCTION SET S3C2440A RISC MICROPROCESSOR 3-10 The instruction produces a result by performing a specified arithmetic or logical operatio

S3C2440A RISC MICROPROCESSOR ARM INSTRUCTION SET 3-11 CPSR FLAGS The data processing operations can be classified as logical or arithmetic. The

ARM INSTRUCTION SET S3C2440A RISC MICROPROCESSOR 3-12 SHIFTS When the second operand is specified to be a shifted register, the operation of the

PRODUCT OVERVIEW S3C2440A RISC MICROPROCESSOR 1-6 PIN ASSIGNMENTS BOTTOM VIEWUTRPNMLKJHGFEDCBA1234567891011121314151617 Figure 1-2. S3C2440A Pin

S3C2440A RISC MICROPROCESSOR ARM INSTRUCTION SET 3-13 31Contents of RmValue of Operand 20carry out4500000 Figure 3-7. Logical Shift Right The fo

ARM INSTRUCTION SET S3C2440A RISC MICROPROCESSOR 3-14 Rotate right (ROR) operations reuse the bits which "overshoot" in a logical shif

S3C2440A RISC MICROPROCESSOR ARM INSTRUCTION SET 3-15 Register Specified Shift Amount Only the least significant byte of the contents of Rs is u

ARM INSTRUCTION SET S3C2440A RISC MICROPROCESSOR 3-16 IMMEDIATE OPERAND ROTATES The immediate operand rotate field is a 4 bit unsigned integer w

S3C2440A RISC MICROPROCESSOR ARM INSTRUCTION SET 3-17 ASSEMBLER SYNTAX •••• MOV,MVN (single operand instructions). <opcode>{cond}{S} Rd,&

ARM INSTRUCTION SET S3C2440A RISC MICROPROCESSOR 3-18 PSR TRANSFER (MRS, MSR) The instruction is only executed if the condition is true. The var

S3C2440A RISC MICROPROCESSOR ARM INSTRUCTION SET 3-19 MSR (transfer register contents or immediate value to PSR flag bits only)Cond Source opera

ARM INSTRUCTION SET S3C2440A RISC MICROPROCESSOR 3-20 RESERVED BITS Only twelve bits of the PSR are defined in ARM920T (N,Z,C,V,I,F, T & M[4

S3C2440A RISC MICROPROCESSOR ARM INSTRUCTION SET 3-21 ASSEMBLY SYNTAX •••• MRS - transfer PSR contents to a register MRS{cond} Rd,<psr>

ARM INSTRUCTION SET S3C2440A RISC MICROPROCESSOR 3-22 MULTIPLY AND MULTIPLY-ACCUMULATE (MUL, MLA) The instruction is only executed if the condit

S3C2440A RISC MICROPROCESSOR PRODUCT OVERVIEW 1-7 Table 1-1. 289-Pin FBGA Pin Assignments – Pin Number Order (Sheet 1 of 3) Pin Number Pin Name

S3C2440A RISC MICROPROCESSOR ARM INSTRUCTION SET 3-23 If the Operands Are Interpreted as Signed Operand A has the value -10, operand B has the v

ARM INSTRUCTION SET S3C2440A RISC MICROPROCESSOR 3-24 CPSR FLAGS Setting the CPSR flags is optional, and is controlled by the S bit in the instr

S3C2440A RISC MICROPROCESSOR ARM INSTRUCTION SET 3-25 MULTIPLY LONG AND MULTIPLY-ACCUMULATE LONG (MULL, MLAL) The instruction is only executed i

ARM INSTRUCTION SET S3C2440A RISC MICROPROCESSOR 3-26 OPERAND RESTRICTIONS • R15 must not be used as an operand or as a destination register. •

S3C2440A RISC MICROPROCESSOR ARM INSTRUCTION SET 3-27 ASSEMBLER SYNTAX Table 3-5. Assembler Syntax Descriptions Mnemonic Description Purpose UMU

ARM INSTRUCTION SET S3C2440A RISC MICROPROCESSOR 3-28 SINGLE DATA TRANSFER (LDR, STR) The instruction is only executed if the condition is true.

S3C2440A RISC MICROPROCESSOR ARM INSTRUCTION SET 3-29 OFFSETS AND AUTO-INDEXING The offset from the base may be either a 12 bit unsigned binary

ARM INSTRUCTION SET S3C2440A RISC MICROPROCESSOR 3-30 LDR from word aligned addressA+3AA+2A+1memory241680ABCDregister241680ABCDLDR from address

S3C2440A RISC MICROPROCESSOR ARM INSTRUCTION SET 3-31 USE OF R15 Write-back must not be specified if R15 is specified as the base register (Rn).

ARM INSTRUCTION SET S3C2440A RISC MICROPROCESSOR 3-32 ASSEMBLER SYNTAX <LDR|STR>{cond}{B}{T} Rd,<Address> where: LDR Load from

PRODUCT OVERVIEW S3C2440A RISC MICROPROCESSOR 1-8 Table 1-1. 289-Pin FBGA Pin Assignments – Pin Number Order (Sheet 2 of 3) Pin Number Pin Name

S3C2440A RISC MICROPROCESSOR ARM INSTRUCTION SET 3-33 EXAMPLES STR R1,[R2,R4]! ; Store R1 at R2+R4 (both of which are registers) ;

ARM INSTRUCTION SET S3C2440A RISC MICROPROCESSOR 3-34 HALFWORD AND SIGNED DATA TRANSFER (LDRH/STRH/LDRSB/LDRSH) The instruction is only executed

S3C2440A RISC MICROPROCESSOR ARM INSTRUCTION SET 3-35 31 27 19 15Cond28 16 11122123120LRn Rd[3:0] Immediate Offset (Low Nibble)[6][5] S H 0 0 =

ARM INSTRUCTION SET S3C2440A RISC MICROPROCESSOR 3-36 HALFWORD LOAD AND STORES Setting S=0 and H=1 may be used to transfer unsigned Half-words b

S3C2440A RISC MICROPROCESSOR ARM INSTRUCTION SET 3-37 Big-Endian Configuration A signed byte load (LDRSB) expects data on data bus inputs 31 thr

ARM INSTRUCTION SET S3C2440A RISC MICROPROCESSOR 3-38 ASSEMBLER SYNTAX <LDR|STR>{cond}<H|SH|SB> Rd,<address> LDR Load fro

S3C2440A RISC MICROPROCESSOR ARM INSTRUCTION SET 3-39 EXAMPLES LDRH R1,[R2,-R3]! ; Load R1 from the contents of the halfword address

ARM INSTRUCTION SET S3C2440A RISC MICROPROCESSOR 3-40 BLOCK DATA TRANSFER (LDM, STM) The instruction is only executed if the condition is true.

S3C2440A RISC MICROPROCESSOR ARM INSTRUCTION SET 3-41 ADDRESSING MODES The transfer addresses are determined by the contents of the base registe

ARM INSTRUCTION SET S3C2440A RISC MICROPROCESSOR 3-42 Rn1R1R12R53R1R54R7Rn0x100C0x10000x0FF40x100C0x10000x0FF40x100C0x10000x0FF40x100C0x10000x0F