Samsung S3F84B8 User Manual

S3F84B8 8-bit CMOS Microcontrollers Revision 1.00 June 2010 UUsseerr''ss MMaannuuaall  2010 Samsung Electronics Co., Ltd

19 EMBEDDED FLASH MEMORY INTERFACE ...19-1 19.1 Overview of Embedded Flash Memory Interface...

S3F84B8_UM_REV 1.00 4 CONTROL REGISTERS 4-36 4.1.39 TACON — TIMER A CONTROL REGISTER: E1H, BANK1 Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 R

S3F84B8_UM_REV 1.00 4 CONTROL REGISTERS 4-37 4.1.40 TAPS — TA PRE-SCALAR REGISTER: E2H, BANK1 Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 RESE

S3F84B8_UM_REV 1.00 4 CONTROL REGISTERS 4-38 4.1.41 TCCON — TIMER C CONTROL REGISTER: E5H, BANK1 Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 R

S3F84B8_UM_REV 1.00 4 CONTROL REGISTERS 4-39 4.1.42 TCPS — TC PRE-SCALAR REGISTER: E6H, BANK1 Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 RESE

S3F84B8_UM_REV 1.00 4 CONTROL REGISTERS 4-40 4.1.43 TDCON — TIMER D CONTROL REGISTER: E9H, BANK1 Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 R

S3F84B8_UM_REV 1.00 4 CONTROL REGISTERS 4-41 4.1.44 TDPS — TD PRE-SCALAR REGISTER: EAH, BANK1 Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 RESE

S3F84B8_UM_REV 1.00 5 INTERRUPT STRUCTURE 5-1 5 INTERRUPT STRUCTURE 5.1 OVERVIEW OF INTERRUPT STRUCTURE The interrupt structure in S3C8/S3F8 ser

S3F84B8_UM_REV 1.00 5 INTERRUPT STRUCTURE 5-2 5.1.4 INTERRUPT TYPES The three components of the S3C8/S3F8 interrupt structure—levels, vectors, an

S3F84B8_UM_REV 1.00 5 INTERRUPT STRUCTURE 5-3 5.1.5 S3F84B8 INTERRUPT STRUCTURE The S3F84B8 microcontroller supports 17 interrupt sources. Every

S3F84B8_UM_REV 1.00 5 INTERRUPT STRUCTURE 5-4 5.1.5.1 Interrupt Vector Addresses All interrupt vector addresses for the S3F84B8 interrupt structu

List of Figures Figure Title Page Number Number Figure 1-1 S3F84B8 Block Diagram ...

S3F84B8_UM_REV 1.00 5 INTERRUPT STRUCTURE 5-5 5.1.6 SYSTEM-LEVEL INTERRUPT CONTROL REGISTERS In addition to the control registers for specific in

S3F84B8_UM_REV 1.00 5 INTERRUPT STRUCTURE 5-6 5.1.7 INTERRUPT PROCESSING CONTROL POINTS Interrupt processing can be controlled in two ways: globa

S3F84B8_UM_REV 1.00 5 INTERRUPT STRUCTURE 5-7 5.1.8 PERIPHERAL INTERRUPT CONTROL REGISTERS For each interrupt source, there is one or more corres

S3F84B8_UM_REV 1.00 5 INTERRUPT STRUCTURE 5-8 5.1.9 SYSTEM MODE REGISTER (SYM) The system mode register, SYM (DEH, Set1), is used to enable and d

S3F84B8_UM_REV 1.00 5 INTERRUPT STRUCTURE 5-9 5.1.10 INTERRUPT MASK REGISTER (IMR) The interrupt mask register, IMR (DDH, Set1) is used to enable

S3F84B8_UM_REV 1.00 5 INTERRUPT STRUCTURE 5-10 5.1.11 INTERRUPT PRIORITY REGISTER (IPR) The interrupt priority register, IPR (FFH, Set1, Bank0),

S3F84B8_UM_REV 1.00 5 INTERRUPT STRUCTURE 5-11 Interrupt Priority Register (IPR)FFH, Set1, Bank0, R/W.7 .6 .5 .4 .3 .2 .1 .0MSB LSBGroup A0 = IRQ0

S3F84B8_UM_REV 1.00 5 INTERRUPT STRUCTURE 5-12 5.1.12 INTERRUPT REQUEST REGISTER (IRQ) You can poll bit values in the interrupt request register,

S3F84B8_UM_REV 1.00 5 INTERRUPT STRUCTURE 5-13 5.1.13 INTERRUPT PENDING FUNCTION TYPES 5.1.13.1 Overview of Interrupt Pending Function Types The

S3F84B8_UM_REV 1.00 5 INTERRUPT STRUCTURE 5-14 5.1.14 INTERRUPT SOURCE POLLING SEQUENCE The interrupt request polling and servicing sequence is a

Figure 5-1 S3C8/S3F8 Series Interrupt Types...

S3F84B8_UM_REV 1.00 5 INTERRUPT STRUCTURE 5-15 5.1.16 GENERATING INTERRUPT VECTOR ADDRESSES The interrupt vector area in the ROM (00H–FFH) contai

S3F84B8_UM_REV 1.00 5 INTERRUPT STRUCTURE 5-16 5.1.18 INSTRUCTION POINTER (IP) The instruction pointer (IP) is adopted by all the S3C8/S3F8 serie

S3F84B8_UM_REV 1.00 5 INTERRUPT STRUCTURE 5-17 5.1.20 PROCEDURE FOR INITIATING FAST INTERRUPTS To initiate fast interrupt processing, follow thes

S3F84B8_UM_REV 1.00 6 INSTRUCTION SET 6-1 6 INSTRUCTION SET 6.1 OVERVIEW OF INSTRUCTION SET The SAM8RC instruction set is specifically design

S3F84B8_UM_REV 1.00 6 INSTRUCTION SET 6-2 Table 6-1 Instruction Group Summary Mnemonic Operands Instruction Load Instructions CLR dst Cle

S3F84B8_UM_REV 1.00 6 INSTRUCTION SET 6-3 Mnemonic Operands Instruction COM dst Complement OR dst,src Logical OR XOR dst,src Logical exclusi

S3F84B8_UM_REV 1.00 6 INSTRUCTION SET 6-4 Mnemonic Operands Instruction CCF Complement carry flag DI Disable interrupts EI Enable interr

S3F84B8_UM_REV 1.00 6 INSTRUCTION SET 6-5 6.2 FLAGS REGISTER (FLAGS) The flags register (FLAGS) contains eight bits that describe current status

S3F84B8_UM_REV 1.00 6 INSTRUCTION SET 6-6 6.2.1 FLAG DESCRIPTIONS C Carry Flag (FLAGS.7) The C flag is set to “1” if the result from an arith

S3F84B8_UM_REV 1.00 6 INSTRUCTION SET 6-7 6.2.2 INSTRUCTION SET NOTATION Table 6-2 Flag Notation Conventions Flag Description C Carry flag

Figure 13-1 A/D Converter Control Register (ADCON) ... 13-

S3F84B8_UM_REV 1.00 6 INSTRUCTION SET 6-8 Table 6-4 Instruction Notation Conventions Notation Description Actual Operand Range cc Condition

S3F84B8_UM_REV 1.00 6 INSTRUCTION SET 6-9 Table 6-5 Opcode Quick Reference OPCODE MAP LOWER NIBBLE (HEX) – 0 1 2 3 4 5 6 7 U 0 D

S3F84B8_UM_REV 1.00 6 INSTRUCTION SET 6-10 OPCODE MAP LOWER NIBBLE (HEX) E 3 WFI R 4 SB0 5 SB1 N 6 IDLE I 7 

S3F84B8_UM_REV 1.00 6 INSTRUCTION SET 6-11 6.2.3 CONDITION CODES The opcode of a conditional jump always contains a 4-bit field called the condi

S3F84B8_UM_REV 1.00 6 INSTRUCTION SET 6-12 6.3 INSTRUCTION DESCRIPTIONS This section contains detailed information and programming examples for

S3F84B8_UM_REV 1.00 6 INSTRUCTION SET 6-13 6.3.1 ADC — ADD WITH CARRY ADC dst,src Operation: dst  dst + src + c The source operand,

S3F84B8_UM_REV 1.00 6 INSTRUCTION SET 6-14 6.3.2 ADD — ADD ADD dst,src Operation: dst  dst + src The source operand is added to the d

S3F84B8_UM_REV 1.00 6 INSTRUCTION SET 6-15 6.3.3 AND — LOGICAL AND AND dst,src Operation: dst  dst AND src The source operand is log

S3F84B8_UM_REV 1.00 6 INSTRUCTION SET 6-16 6.3.4 BAND — BIT AND BAND dst,src.b BAND dst.b,src Operation: dst(0)  dst(0) AND src(b)

S3F84B8_UM_REV 1.00 6 INSTRUCTION SET 6-17 6.3.5 BCP — BIT COMPARE BCP dst,src.b Operation: dst(0) – src(b) The specified bit of source

Figure 22-1 Development System Configuration ...

S3F84B8_UM_REV 1.00 6 INSTRUCTION SET 6-18 6.3.6 BITC — BIT COMPLEMENT BITC dst.b Operation: dst(b)  NOT dst(b) This instruction comp

S3F84B8_UM_REV 1.00 6 INSTRUCTION SET 6-19 6.3.7 BITR — BIT RESET BITR dst.b Operation: dst(b)  0 The BITR instruction clears the spe

S3F84B8_UM_REV 1.00 6 INSTRUCTION SET 6-20 6.3.8 BITS — BIT SET BITS dst.b Operation: dst(b)  1 The BITS instruction sets the specifi

S3F84B8_UM_REV 1.00 6 INSTRUCTION SET 6-21 6.3.9 BOR — BIT OR BOR dst,src.b BOR dst.b,src Operation: dst(0)  dst(0) OR src(b) or

S3F84B8_UM_REV 1.00 6 INSTRUCTION SET 6-22 6.3.10 BTJRF — BIT TEST, JUMP RELATIVE ON FALSE BTJRF dst,src.b Operation: If src(b) is a “0”, the

S3F84B8_UM_REV 1.00 6 INSTRUCTION SET 6-23 6.3.11 BTJRT — BIT TEST, JUMP RELATIVE ON TRUE BTJRT dst,src.b Operation: If src(b) is a “1”, then

S3F84B8_UM_REV 1.00 6 INSTRUCTION SET 6-24 6.3.12 BXOR — BIT XOR BXOR dst,src.b BXOR dst.b,src Operation: dst(0)  dst(0) XOR src(b)

S3F84B8_UM_REV 1.00 6 INSTRUCTION SET 6-25 6.3.13 CALL — CALL PROCEDURE CALL dst Operation: SP  SP – 1 @SP  PCL SP  SP –1 @SP

S3F84B8_UM_REV 1.00 6 INSTRUCTION SET 6-26 6.3.14 CCF — COMPLEMENT CARRY FLAG CCF Operation: C  NOT C The carry flag (C) is complement

S3F84B8_UM_REV 1.00 6 INSTRUCTION SET 6-27 6.3.15 CLR — CLEAR CLR dst Operation: dst  “0” The destination location is cleared to “0”.

List of Tables Table Title Page Number Number Table 1-1 Pin Descriptions (20-DIP/20-SOP) in S3F84B8...

S3F84B8_UM_REV 1.00 6 INSTRUCTION SET 6-28 6.3.16 COM — COMPLEMENT COM dst Operation: dst  NOT dst The contents of destination locat

S3F84B8_UM_REV 1.00 6 INSTRUCTION SET 6-29 6.3.17 CP — COMPARE CP dst,src Operation: dst – src The source operand is compared to (sub

S3F84B8_UM_REV 1.00 6 INSTRUCTION SET 6-30 6.3.18 CPIJE — COMPARE, INCREMENT, AND JUMP ON EQUAL CPIJE dst,src,RA Operation: If dst – src = “0

S3F84B8_UM_REV 1.00 6 INSTRUCTION SET 6-31 6.3.19 CPIJNE — COMPARE, INCREMENT, AND JUMP ON NON-EQUAL CPIJNE dst,src,RA Operation: If dst – src

S3F84B8_UM_REV 1.00 6 INSTRUCTION SET 6-32 6.3.20 DA — DECIMAL ADJUST DA dst Operation: dst  DA dst The destination operand is adju

S3F84B8_UM_REV 1.00 6 INSTRUCTION SET 6-33 6.3.21 DA — DECIMAL ADJUST (CONTINUED) DA Example: Given that working register R0 contains the valu

S3F84B8_UM_REV 1.00 6 INSTRUCTION SET 6-34 6.3.22 DEC — DECREMENT DEC dst Operation: dst  dst – 1 The contents of the destination ope

S3F84B8_UM_REV 1.00 6 INSTRUCTION SET 6-35 6.3.23 DECW — DECREMENT WORD DECW dst Operation: dst  dst – 1 The contents of destination

S3F84B8_UM_REV 1.00 6 INSTRUCTION SET 6-36 6.3.24 DI — DISABLE INTERRUPTS DI Operation: SYM (0)  0 Bit zero of the system mode control

S3F84B8_UM_REV 1.00 6 INSTRUCTION SET 6-37 6.3.25 DIV — DIVIDE (UNSIGNED) DIV dst,src Operation: dst ÷ src dst (UPPER)  REMAINDER

Table 22-1 TB84B8 Components...

S3F84B8_UM_REV 1.00 6 INSTRUCTION SET 6-38 6.3.26 DJNZ — DECREMENT AND JUMP IF NON-ZERO DJNZ r,dst Operation: r  r – 1 If r  0, PC

S3F84B8_UM_REV 1.00 6 INSTRUCTION SET 6-39 6.3.27 EI — ENABLE INTERRUPTS EI Operation: SYM (0)  1 An EI instruction sets the bit zero of

S3F84B8_UM_REV 1.00 6 INSTRUCTION SET 6-40 6.3.28 ENTER — ENTER ENTER Operation: SP  SP – 2 @SP  IP IP  PC PC  @IP IP 

S3F84B8_UM_REV 1.00 6 INSTRUCTION SET 6-41 EXIT — Exit EXIT Operation: IP  @SP SP  SP + 2 PC  @IP IP  IP + 2 This ins

S3F84B8_UM_REV 1.00 6 INSTRUCTION SET 6-42 6.3.29 IDLE — IDLE OPERATION IDLE Operation: The IDLE instruction stops the CPU clock while a

S3F84B8_UM_REV 1.00 6 INSTRUCTION SET 6-43 6.3.30 INC — INCREMENT INC dst Operation: dst  dst + 1 The contents of the destination o

S3F84B8_UM_REV 1.00 6 INSTRUCTION SET 6-44 6.3.31 INCW — INCREMENT WORD INCW dst Operation: dst  dst + 1 The contents of destination

S3F84B8_UM_REV 1.00 6 INSTRUCTION SET 6-45 6.3.32 IRET — INTERRUPT RETURN IRET IRET (Normal) IRET (Fast) Operation: FLAGS  @SP PC  I

S3F84B8_UM_REV 1.00 6 INSTRUCTION SET 6-46 6.3.33 JP — JUMP JP cc,dst (Conditional) JP dst (Unconditional) Operation: If cc is true,

S3F84B8_UM_REV 1.00 6 INSTRUCTION SET 6-47 6.3.34 JR — JUMP RELATIVE JR cc,dst Operation: If cc is true, PC  PC + dst. If the con

List of Examples Example Title Page Number Number Example 2-1 Setting the Register Pointers ...

S3F84B8_UM_REV 1.00 6 INSTRUCTION SET 6-48 6.3.35 LD — LOAD LD dst,src Operation: dst  src The contents of the source are loaded in

S3F84B8_UM_REV 1.00 6 INSTRUCTION SET 6-49 6.3.36 LD — LOAD (CONTINUED) LD Examples: Given R0 = 01H, R1 = 0AH, register 00H = 01H, register 01H

S3F84B8_UM_REV 1.00 6 INSTRUCTION SET 6-50 6.3.37 LDB — LOAD BIT LDB dst,src.b LDB dst.b,src Operation: dst(0)  src(b) or dst(b

S3F84B8_UM_REV 1.00 6 INSTRUCTION SET 6-51 6.3.38 LDC/LDE — LOAD MEMORY LDC/LDE dst,src Operation: dst  src This instruction loads a by

S3F84B8_UM_REV 1.00 6 INSTRUCTION SET 6-52 6.3.39 LDC/LDE — LOAD MEMORY (CONTINUED) LDC/LDE Examples: Given R0 = 11H, R1 = 34H, R2 = 01H, R3 =

S3F84B8_UM_REV 1.00 6 INSTRUCTION SET 6-53 6.3.40 LDCD/LDED — LOAD MEMORY AND DECREMENT LDCD/LDED dst,src Operation: dst  src rr  rr –

S3F84B8_UM_REV 1.00 6 INSTRUCTION SET 6-54 6.3.41 LDCI/LDEI — LOAD MEMORY AND INCREMENT LDCI/LDEI dst,src Operation: dst  src rr  rr

S3F84B8_UM_REV 1.00 6 INSTRUCTION SET 6-55 6.3.42 LDCPD/LDEPD — LOAD MEMORY WITH PRE-DECREMENT LDCPD/ LDEPD dst,src Operation: rr  rr – 1

S3F84B8_UM_REV 1.00 6 INSTRUCTION SET 6-56 6.3.43 LDCPI/LDEPI — LOAD MEMORY WITH PRE-INCREMENT LDCPI/ LDEPI dst,src Operation: rr  rr + 1

S3F84B8_UM_REV 1.00 6 INSTRUCTION SET 6-57 6.3.44 LDW — LOAD WORD LDW dst,src Operation: dst  src The contents of source (word) are l

S3F84B8_UM_REV 1.00 1 OVERVIEW OF S3F84B8 MICROCONTROLLER 1-1 1 OVERVIEW OF S3F84B8 MICROCONTROLLER 1.1 S3C8-SERIES MICROCONTROLLERS Samsung’s S

S3F84B8_UM_REV 1.00 6 INSTRUCTION SET 6-58 6.3.45 MULT — MULTIPLY (UNSIGNED) MULT dst,src Operation: dst  dst  src The 8-bit desti

S3F84B8_UM_REV 1.00 6 INSTRUCTION SET 6-59 6.3.46 NEXT — NEXT NEXT Operation: PC  @ IP IP  IP + 2 The NEXT instruction is useful

S3F84B8_UM_REV 1.00 6 INSTRUCTION SET 6-60 6.3.47 NOP — NO OPERATION NOP Operation: No action is performed when the CPU executes this instructi

S3F84B8_UM_REV 1.00 6 INSTRUCTION SET 6-61 6.3.48 OR — LOGICAL OR OR dst,src Operation: dst  dst OR src The source operand is log

S3F84B8_UM_REV 1.00 6 INSTRUCTION SET 6-62 6.3.49 POP — POP FROM STACK POP dst Operation: dst  @SP SP  SP + 1 The contents o

S3F84B8_UM_REV 1.00 6 INSTRUCTION SET 6-63 6.3.50 POPUD — POP USER STACK (DECREMENTING) POPUD dst,src Operation: dst  src IR  IR – 1

S3F84B8_UM_REV 1.00 6 INSTRUCTION SET 6-64 6.3.51 POPUI — POP USER STACK (INCREMENTING) POPUI dst,src Operation: dst  src IR  IR + 1

S3F84B8_UM_REV 1.00 6 INSTRUCTION SET 6-65 6.3.52 PUSH — PUSH TO STACK PUSH src Operation: SP  SP – 1 @SP  src A PUSH instru

S3F84B8_UM_REV 1.00 6 INSTRUCTION SET 6-66 6.3.53 PUSHUD — PUSH USER STACK (DECREMENTING) PUSHUD dst,src Operation: IR  IR – 1 dst  s

S3F84B8_UM_REV 1.00 6 INSTRUCTION SET 6-67 6.3.54 PUSHUI — PUSH USER STACK (INCREMENTING) PUSHUI dst,src Operation: IR  IR + 1 dst 

S3F84B8_UM_REV 1.00 1 OVERVIEW OF S3F84B8 MICROCONTROLLER 1-2 1.1.2 KEY FEATURES OF S3F84B8 The key features of S3F84B8 include: CPU  SAM8RC CPU

S3F84B8_UM_REV 1.00 6 INSTRUCTION SET 6-68 6.3.55 RCF — RESET CARRY FLAG RCF RCF Operation: C  0 The carry flag is cleared to logic z

S3F84B8_UM_REV 1.00 6 INSTRUCTION SET 6-69 6.3.56 RET — RETURN RET Operation: PC  @SP SP  SP + 2 Typically, the RET instruction

S3F84B8_UM_REV 1.00 6 INSTRUCTION SET 6-70 6.3.57 RL — ROTATE LEFT RL dst Operation: C  dst (7) dst (0)  dst (7) dst (n + 1)

S3F84B8_UM_REV 1.00 6 INSTRUCTION SET 6-71 6.3.58 RLC — ROTATE LEFT THROUGH CARRY RLC dst Operation: dst (0)  C C  dst (7) dst (

S3F84B8_UM_REV 1.00 6 INSTRUCTION SET 6-72 6.3.59 RR — ROTATE RIGHT RR dst Operation: C  dst (0) dst (7)  dst (0) dst (n  d

S3F84B8_UM_REV 1.00 6 INSTRUCTION SET 6-73 6.3.60 RRC — ROTATE RIGHT THROUGH CARRY RRC dst Operation: dst (7)  C C  dst (0) dst (n

S3F84B8_UM_REV 1.00 6 INSTRUCTION SET 6-74 6.3.61 SB0 — SELECT BANK 0 SB0 Operation: BANK  0 The SB0 instruction clears the bank addres

S3F84B8_UM_REV 1.00 6 INSTRUCTION SET 6-75 6.3.63 SBC — SUBTRACT WITH CARRY SBC dst,src Operation: dst  dst – src – c The source op

S3F84B8_UM_REV 1.00 6 INSTRUCTION SET 6-76 6.3.64 SCF — SET CARRY FLAG SCF Operation: C  1 The carry flag (C) is set to logic one, rega

S3F84B8_UM_REV 1.00 6 INSTRUCTION SET 6-77 6.3.65 SRA — SHIFT RIGHT ARITHMETIC SRA dst Operation: dst (7)  dst (7) C  dst (0) ds

Important Notice The information in this publication has been carefully checked and is believed to be entirely accurate at the time of publi

S3F84B8_UM_REV 1.00 1 OVERVIEW OF S3F84B8 MICROCONTROLLER 1-3 10-bit IH PWM  10-bit IH specific PWM 1-channel  Cooperate with CMPs  Anti-mis-

S3F84B8_UM_REV 1.00 6 INSTRUCTION SET 6-78 6.3.66 RP/SRP0/SRP1 — SET REGISTER POINTER SRP src SRP0 src SRP1 src Operation: If src (1) = 1

S3F84B8_UM_REV 1.00 6 INSTRUCTION SET 6-79 6.3.67 STOP — STOP OPERATION STOP Operation: The STOP instruction stops both the CPU clock and sy

S3F84B8_UM_REV 1.00 6 INSTRUCTION SET 6-80 6.3.68 SUB — SUBTRACT SUB dst,src Operation: dst  dst – src Once source operand is subtrac

S3F84B8_UM_REV 1.00 6 INSTRUCTION SET 6-81 6.3.69 SWAP — SWAP NIBBLES SWAP dst Operation: dst (0 – 3)  dst (4 – 7) The contents of

S3F84B8_UM_REV 1.00 6 INSTRUCTION SET 6-82 6.3.70 TCM — TEST COMPLEMENT UNDER MASK TCM dst,src Operation: (NOT dst) AND src This instru

S3F84B8_UM_REV 1.00 6 INSTRUCTION SET 6-83 6.3.71 TM — TEST UNDER MASK TM dst,src Operation: dst AND src This instruction tests sel

S3F84B8_UM_REV 1.00 6 INSTRUCTION SET 6-84 6.3.72 WFI — WAIT FOR INTERRUPT WFI Operation: The CPU is halted until an interrupt occurs; eve

S3F84B8_UM_REV 1.00 6 INSTRUCTION SET 6-85 6.3.73 XOR — LOGICAL EXCLUSIVE OR XOR dst,src Operation: dst  dst XOR src Source operand

S3F84B8_UM_REV 1.00 7 CLOCK CIRCUIT 7-1 7 CLOCK CIRCUIT 7.1 OVERVIEW OF CLOCK CIRCUIT Using the Smart option (3FH.1– .0 in ROM), you can select

S3F84B8_UM_REV 1.00 7 CLOCK CIRCUIT 7-2 7.1.1 CLOCK STATUS DURING POWER-DOWN MODES The two power-down modes, Stop and Idle, affect clock oscillat

S3F84B8_UM_REV 1.00 1 OVERVIEW OF S3F84B8 MICROCONTROLLER 1-4 Built-in RESET Circuit (LVR)  Low-voltage check to reset system  VLVR = 1.9/2.3/3

S3F84B8_UM_REV 1.00 7 CLOCK CIRCUIT 7-3 MUXSelectedOSCNoiseFilterOscillatorWake-upOscillatorStopCLKCON.7INT PinCLKCON.4-.31/21/16MUXStopInstructio

S3F84B8_UM_REV 1.00 8 RESET AND POWER-DOWN 8-1 8 RESET AND POWER-DOWN 8.1 OVERVIEW OF SYSTEM RESET Using the Smart option (3FH.7 in ROM), you ca

S3F84B8_UM_REV 1.00 8 RESET AND POWER-DOWN 8-2 +-VREFBGR VDDVREFVIN VDDN.FInternal SystemRESETBWhen the VDD levelis lower than VLVRComparatorNOTES

S3F84B8_UM_REV 1.00 8 RESET AND POWER-DOWN 8-3 8.1.1 MCU INITIALIZATION SEQUENCE The following sequence of events occurs during a Reset operation

S3F84B8_UM_REV 1.00 8 RESET AND POWER-DOWN 8-4 8.2 POWER-DOWN MODES 8.2.1 STOP MODE Stop mode is invoked by the STOP (opcode 7FH) instruction. I

S3F84B8_UM_REV 1.00 8 RESET AND POWER-DOWN 8-5 8.2.1.3 Idle Mode Idle mode is invoked by the IDLE (opcode 6FH) instruction. In Idle mode, the CPU

S3F84B8_UM_REV 1.00 8 RESET AND POWER-DOWN 8-6 8.2.2 HARDWARE RESET VALUES Figure 8-1 shows the reset values of the CPU and system registers, per

S3F84B8_UM_REV 1.00 8 RESET AND POWER-DOWN 8-7 Address and Location RESET Value (Bit) Register Name Mnemonic Address R/W 7 6 5 4 3 2 1 0Comp

S3F84B8_UM_REV 1.00 8 RESET AND POWER-DOWN 8-8 Table 8-2 System and Peripheral Control Registers Set1 Bank1 Address and Location RESET Value

S3F84B8_UM_REV 1.00 9 I/O PORTS 9-1 9 I/O PORTS 9.1 OVERVIEW OF I/O PORTS The S3F84B8 microcontroller has three bit-programmable I/O ports (P0,

S3F84B8_UM_REV 1.00 1 OVERVIEW OF S3F84B8 MICROCONTROLLER 1-5 1.1.3 BLOCK DIAGRAM OF S3F84B8 Figure 1-1 shows the block diagram of S3F84B8. I/ O

S3F84B8_UM_REV 1.00 9 I/O PORTS 9-2 9.1.1.1 Port 0 Port 0 is a 6-bit I/O port that you can use in two ways:  General-purpose I/O  Alternative f

S3F84B8_UM_REV 1.00 9 I/O PORTS 9-3 Port 0 High Control Register (P0CONH)E3H, Set1, Bank0, R/W, Reset value:00HLSBMSB .7 .6 .5 .4 .3 .2 .1 .0.3 .2

S3F84B8_UM_REV 1.00 9 I/O PORTS 9-4 Port 0 Low Control Register (P0CONL)E4H, Set1, Bank0, R/W, Reset value:00HLSBMSB.7.6.5.4.3.2.1.0.5 .4 bit No

S3F84B8_UM_REV 1.00 9 I/O PORTS 9-5 Port 0 External Interrupt Register (P0INT)E3H, Set1, Bank0, R/W, Reset value:00HLSBMSB.7.6.5 .4.3.2.1.0Notused

S3F84B8_UM_REV 1.00 9 I/O PORTS 9-6 P0.4/INT3P0.3/INT2Port 0 Interrupt Pending Register (P0PND)E6H, Set1, Bank0, R/W, Reset value: 00H.7 .6 .5 .4

S3F84B8_UM_REV 1.00 9 I/O PORTS 9-7 9.1.1.2 Port 1 Port 1 is a 3-bit I/O port that you can use in two ways:  General-purpose I/O  Alternative f

S3F84B8_UM_REV 1.00 9 I/O PORTS 9-8 Port 1 Control Register (P1CON)E7H, Set1, Bank0, R/W, Reset value:00HLSBMSB.7.6.5.4.3 .2.1.0.5 .4 bit/P1.2/CMP

S3F84B8_UM_REV 1.00 9 I/O PORTS 9-9 9.1.1.3 Port 2 Port 2 is an 8-bit I/O port that you can use in two ways:  General-purpose I/O  Alternative

S3F84B8_UM_REV 1.00 9 I/O PORTS 9-10 Port 2 Control Register, High Byte (P2CONH)E8H, Set1, Bank0, R/W, Reset value:00HLSBMSB.7.6 .5.4.3.2.1.0.7 .6

S3F84B8_UM_REV 1.00 9 I/O PORTS 9-11 Port 2 Control Register, Low Byte (P2CONL)E8H, Set1, Bank0, R/W, Reset value:00HLSBMSB.7.6.5 .4.3.2.1.0.7 .6

S3F84B8_UM_REV 1.00 1 OVERVIEW OF S3F84B8 MICROCONTROLLER 1-6 1.1.4 PIN ASSIGNMENTS Figure 1-2 shows the pin assignments (20-DIP, 20-SOP) in S3

S3F84B8_UM_REV 1.00 10 BASIC TIMER 10-1 10 BASIC TIMER 10.1 OVERVIEW OF BASIC TIMER You can use the basic timer (BT) in two different ways:

S3F84B8_UM_REV 1.00 10 BASIC TIMER 10-2 10.2 BASIC TIMER CONTROL REGISTER (BTCON) The basic timer control register, BTCON, selects the input cloc

S3F84B8_UM_REV 1.00 10 BASIC TIMER 10-3 10.2.1 BASIC TIMER FUNCTION DESCRIPTION 10.2.1.1 Watchdog Timer Function You can program the basic timer

S3F84B8_UM_REV 1.00 10 BASIC TIMER 10-4 Oscillation Stabilization TimeNormal Operating mode0.8 VDDtWAIT = (4096x128)/fOSCBasic timer increment and

S3F84B8_UM_REV 1.00 10 BASIC TIMER 10-5 NOTE: Duration of the oscillator stabilzation wait time, tWAIT, it is released by an interrupt is determin

S3F84B8_UM_REV 1.00 10 BASIC TIMER 10-6 Example 10-1 Configuring the Basic Timer This example shows how to configure the basic timer to sampl

S3F84B8_UM_REV 1.00 11 8-BIT TIMER A 11-1 11 8-BIT TIMER A 11.1 OVERVIEW OF 8-BIT TIMER A The 8-bit Timer A is a general-purpose timer/counter

S3F84B8_UM_REV 1.00 11 8-BIT TIMER A 11-2 11.1.1 FUNCTIONAL DESCRIPTION 11.1.1.1 Timer A Interrupts The Timer A module can generate two interr

S3F84B8_UM_REV 1.00 11 8-BIT TIMER A 11-3 11.1.2 TIMER A CONTROL REGISTER (TACON) You can use the Timer A control register (TACON) for the follow

S3F84B8_UM_REV 1.00 11 8-BIT TIMER A 11-4 NOTE: When the counter clear bit(.5) is set, the 8-bit counter is cleared and it will b

S3F84B8_UM_REV 1.00 1 OVERVIEW OF S3F84B8 MICROCONTROLLER 1-7 1.1.5 PIN DESCRIPTIONS Table 1-1 shows the pin descriptions (20-DIP/20-SOP) in S3F8

S3F84B8_UM_REV 1.00 11 8-BIT TIMER A 11-5 Timer A Prescaler Register (TAPS)E3H, Set1, Bank1, R/WLSBMSB.7.6.5.4.3.2.1.0Reset Value: FFhTimer A clo

S3F84B8_UM_REV 1.00 11 8-BIT TIMER A 11-6 11.1.3 BLOCK DIAGRAM OF TIMER A NOTE: When PWM mode, match signal cannot clear counter .ClearMatchTACON

S3F84B8_UM_REV 1.00 12 TIMER 0 12-1 12 TIMER 0 12.1 ONE 16-BIT TIMER MODE (TIMER 0) The 16-bit Timer 0 is used in one 16-bit Timer mode or two

S3F84B8_UM_REV 1.00 12 TIMER 0 12-2 12.1.2 FUNCTIONAL DESCRIPTION OF ONE 16-BIT TIMER MODE (TIMER 0) 12.1.2.1 Interval Timer Function Timer 0 m

S3F84B8_UM_REV 1.00 12 TIMER 0 12-3 Timer C Control Register (TCCON)E5H, Set1, Bank1, Reset = 00H, R/W.7 .6 .5 .4 .3 .2 .1 .0MSB LSBTimer C Matc

S3F84B8_UM_REV 1.00 12 TIMER 0 12-4 12.1.3 BLOCK DIAGRAM OF TIMER 0 NOTE: When TCCON.7 is '1', one 16-bit Timer 0.ComparatorTCCNT TDCN

S3F84B8_UM_REV 1.00 12 TIMER 0 12-5 12.2 TWO 8-BIT TIMERS MODE (TIMER C AND D) 12.2.1 OVERVIEW OF TWO 8-BIT TIMERS MODE (TIMER C AND D) Timers

S3F84B8_UM_REV 1.00 12 TIMER 0 12-6 TCCON and TDCON are located in address E5H and E9H, Set1 Bank1, and are read/write addressable using register

S3F84B8_UM_REV 1.00 12 TIMER 0 12-7 Timer C Prescaler Register (TCPS)E6H, Set1, Bank1, R/WLSBMSB.7.6.5.4.3.2.1.0Reset Value: 00hTimer C clock sou

S3F84B8_UM_REV 1.00 12 TIMER 0 12-8 Timer B Control Register (TDCON)E9H, Set1, Bank1, Reset = 00H, R/W.7 .6 .5 .4 .3 .2 .1 .0MSB LSBTimer D coun

S3F84B8_UM_REV 1.00 1 OVERVIEW OF S3F84B8 MICROCONTROLLER 1-8 Table 1-2 shows the pin descriptions used to Read/Write the Flash ROM in S3F84B8. T

S3F84B8_UM_REV 1.00 12 TIMER 0 12-9 12.2.3 FUNCTIONAL DESCRIPTION OF TWO 8-BIT TIMERS MODE (TIMER C AND D) 12.2.3.1 Interval Timer Function (Ti

S3F84B8_UM_REV 1.00 12 TIMER 0 12-10 NOTE:When TCCON.7 is '0', two 8-bit timer C/D (Interval mode).TDPS.3-.0PrescalerTCCON.4Comparatorf

S3F84B8_UM_REV 1.00 12 TIMER 0 12-11 12.2.3.2 Pulse Width Modulation Mode (Timer D) Pulse width modulation (PWM) mode allows you to program the

S3F84B8_UM_REV 1.00 13 A/D CONVERTER 13-1 13 A/D CONVERTER 13.1 OVERVIEW OF A/D CONVERTER The 10-bit analog-to-digital (A/D) converter (ADC) m

S3F84B8_UM_REV 1.00 13 A/D CONVERTER 13-2 13.1.1 USING A/D PINS FOR STANDARD DIGITAL INPUT The ADC module’s input pins are alternatively used as

S3F84B8_UM_REV 1.00 13 A/D CONVERTER 13-3 13.1.2 INTERNAL REFERENCE VOLTAGE LEVELS In the ADC function block, the analog input voltage level is c

S3F84B8_UM_REV 1.00 13 A/D CONVERTER 13-4 50 ADC ClockADCON.0 1. . .40 ClockPreviousValueValidDataSet uptime10 clockADDATAH (8-Bit) + ADD

S3F84B8_UM_REV 1.00 13 A/D CONVERTER 13-5 13.1.3 CONVERSION TIMING The A/D conversion process requires four steps (4 clock edges) to convert each

S3F84B8_UM_REV 1.00 13 A/D CONVERTER 13-6 Example 13-1 Configuring A/D Converter ;-----------------<< Interrupt Vector Address >&g

S3F84B8_UM_REV 1.00 14 COMPARATOR 14-1 14 COMPARATOR 14.1 OVERVIEW OF COMPARATOR The S3F84B8 microcontroller has four comparators (Comparator

S3F84B8_UM_REV 1.00 1 OVERVIEW OF S3F84B8 MICROCONTROLLER 1-9 1.1.6 PIN CIRCUITS Figure 1-3 shows the pin circuit type 1 in S3F84B8. P-ChannelN-C

S3F84B8_UM_REV 1.00 14 COMPARATOR 14-2 CMP0 Control Register (CMP0CON)EAH, Set1, Bank0, Reset = 02H, R/W.7 .6 .5 .4 .3 .2 .1 .0MSB LSBCMP0 status

S3F84B8_UM_REV 1.00 14 COMPARATOR 14-3 14.1.1.1.2 Block Diagram of Comparator 0 C0PLR (CMP0CON.4)C0EN (CMP0CON.3)CMP0CON.0PWMCMP0_NCMP0_P+-CMP0QQS

S3F84B8_UM_REV 1.00 14 COMPARATOR 14-4 14.1.1.2 Comparator 1/2/3 Comparator 1, 2, and 3 have the same structure. Their positive input is internal

S3F84B8_UM_REV 1.00 14 COMPARATOR 14-5 CMP1 Control Register (CMP1CON)EBH, Set1, Bank0, Reset = 02H, R/W.7 .6 .5 .4 .3 .2 .1 .0MSB LSBCMP1 status

S3F84B8_UM_REV 1.00 14 COMPARATOR 14-6 CMP3 Control Register (CMP3CON)EDH, Set1, Bank0, Reset = 02H, R/W.7 .6 .5 .4 .3 .2 .1 .0MSB LSBCMP3 status

S3F84B8_UM_REV 1.00 14 COMPARATOR 14-7 14.1.1.2.2 Block Diagram of Comparator 1/2/3 C1/2/3PLR (CMP1/2/3CON.4)C1/2/3EN (CMP1/2/ 3CON.3)PWMCMP0_N+-C

S3F84B8_UM_REV 1.00 15 OPERATIONAL AMPLIFIER 15-1 15 OPERATIONAL AMPLIFIER 15.1 OVERVIEW OF OPERATIONAL AMPLIFIER The S3F84B8 microcontroller

S3F84B8_UM_REV 1.00 15 OPERATIONAL AMPLIFIER 15-2 15.1.2 OPAMP CONTROL REGISTER You can use the OPAMP control register, OPACON, for the following

S3F84B8_UM_REV 1.00 15 OPERATIONAL AMPLIFIER 15-3 15.1.4 REFERENCE CIRCUIT +-OPAMPOA_NADC3(OA_O)OA_PRf 100KR1 10KC 1 102pFCL I02pFNOTE:1. R1 shou

S3F84B8_UM_REV 1.00 16 10-BIT IH-PWM 16-1 16 10-BIT IH-PWM 16.1 OVERVIEW OF 10-BIT IH-PWM The S3F84B8 microcontroller has a 10-bit IH-PWM circui

S3F84B8_UM_REV 1.00 1 OVERVIEW OF S3F84B8 MICROCONTROLLER 1-10 Figure 1-5 shows the pin circuit type 1-1 (P1.0-1.2, P2.0-2.2, P2.4-2.7) in S3F84B8

S3F84B8_UM_REV 1.00 16 10-BIT IH-PWM 16-2 16.2 FUNCTIONAL DESCRIPTION OF 10-BIT IH-PWM 16.2.1 PWM The 10-bit PWM circuit has the following compo

S3F84B8_UM_REV 1.00 16 10-BIT IH-PWM 16-3 16.2.3 PWM FUNCTIONAL DESCRIPTION By disabling the linkage of CMPs and PWM (setting PWMCCON to ‘00H’),

S3F84B8_UM_REV 1.00 16 10-BIT IH-PWM 16-4 16.2.4 PWM CONTROL REGISTER (PWMCON) The control register for the PWM module, PWMCON, is located at reg

S3F84B8_UM_REV 1.00 16 10-BIT IH-PWM 16-5 16.2.5 PWM CMP LINKAGE CONTROL REGISTER (PWMCCON) The control register for linkage of CMP and PWM modul

S3F84B8_UM_REV 1.00 16 10-BIT IH-PWM 16-6 16.2.6 BLOCK DIAGRAM OF PWM MODULE CLR&STOverflow10-bit Up-Counter(Read Only)10-bit ComparatorPWM B

S3F84B8_UM_REV 1.00 16 10-BIT IH-PWM 16-7 PWM CLKCMP0 OUTPUTPWM OUTPUT PWMDATAPWMDATAIGBT ONIGBT OFFIGBT ONIGBT OFF4/fpwmclkPWMCCON.1-.0 = 01Delay

S3F84B8_UM_REV 1.00 16 10-BIT IH-PWM 16-8 Hard Lock triggerPWM OUTPUTPWM LOCKIGBT ONIGBT OFFNOTE: Because CMP1/2/3 is asynchronous, lock action ha

S3F84B8_UM_REV 1.00 17 PROGRAMMABLE BUZZER 17-1 17 PROGRAMMABLE BUZZER 17.1 OVERVIEW OF PROGRAMMABLE BUZZER The S3F84B8 microcontroller has a

S3F84B8_UM_REV 1.00 17 PROGRAMMABLE BUZZER 17-2 17.2.2 BUZ FREQUENCY TABLE (@4MHZ) Table 17-1 Buzzer Frequency Table (@4MHz) Output Frequenc

S3F84B8_UM_REV 1.00 17 PROGRAMMABLE BUZZER 17-3 ClearMatchBUZCON.7-.6fosc/128BUZOUT(P0. 3)Data Bus8MUX5-bit Up-Counter5-bit ComparatorBUZ Buffer R

S3F84B8_UM_REV 1.00 1 OVERVIEW OF S3F84B8 MICROCONTROLLER 1-11 Figure 1-6 shows the Pin Circuit Type 1-2 (P2.3) in S3F84B8. VDDI/ODigital InputPul

S3F84B8_UM_REV 1.00 18 FLASH MCU ROM 18-1 18 FLASH MCU ROM 18.1 OVERVIEW OF FLASH MCU ROM The S3F84B8 single-chip CMOS microcontroller has an on

S3F84B8_UM_REV 1.00 18 FLASH MCU ROM 18-2 Table 18-1 Descriptions of Pins Used to Read/Write the Flash ROM Main Chip During Programming Pin

S3F84B8_UM_REV 1.00 19 EMBEDDED FLASH MEMORY INTERFACE 19-1 19 EMBEDDED FLASH MEMORY INTERFACE 19.1 OVERVIEW OF EMBEDDED FLASH MEMORY INTERFACE

S3F84B8_UM_REV 1.00 19 EMBEDDED FLASH MEMORY INTERFACE 19-2 19.1.3 USER PROGRAM MODE This mode supports sector erase, byte programming, byte read

S3F84B8_UM_REV 1.00 19 EMBEDDED FLASH MEMORY INTERFACE 19-3 19.1.5 FLASH MEMORY CONTROL REGISTERS (USER PROGRAM MODE) 19.1.5.1 Flash Memory Cont

S3F84B8_UM_REV 1.00 19 EMBEDDED FLASH MEMORY INTERFACE 19-4 19.1.5.3 Flash Memory Sector Address Registers There are two sector address registe

S3F84B8_UM_REV 1.00 19 EMBEDDED FLASH MEMORY INTERFACE 19-5 19.1.6 SECTOR ERASE You can erase the flash memory partially by using sector erase fu

S3F84B8_UM_REV 1.00 19 EMBEDDED FLASH MEMORY INTERFACE 19-6 Sector Erase Procedure in User Program Mode To erase sector in User Program mode, foll

S3F84B8_UM_REV 1.00 19 EMBEDDED FLASH MEMORY INTERFACE 19-7 Example 19-1 Sector Erase Case 1. Erase one sector   ERASE_ONESECTOR

S3F84B8_UM_REV 1.00 19 EMBEDDED FLASH MEMORY INTERFACE 19-8 19.1.7 PROGRAMMING Flash memory is programmed in one-byte unit after sector erase.

S3F84B8_UM_REV 1.00 1 OVERVIEW OF S3F84B8 MICROCONTROLLER 1-12 Figure 1-7 shows the Pin Circuit Type 1-3 (P0.3, P0.4, P0.6) in S3F84B8. I/OOutput

S3F84B8_UM_REV 1.00 19 EMBEDDED FLASH MEMORY INTERFACE 19-9 SB1Start; Select Bank1; User Program Mode Enable; Set Secotr Base Address; Write dat

S3F84B8_UM_REV 1.00 19 EMBEDDED FLASH MEMORY INTERFACE 19-10 SB1Start; Select Bank1; User Program Mode Enable; Set Secotr Base Address; Write da

S3F84B8_UM_REV 1.00 19 EMBEDDED FLASH MEMORY INTERFACE 19-11 Example 19-2 Programming Case1. 1-Byte Programming   WR_BYTE:

S3F84B8_UM_REV 1.00 19 EMBEDDED FLASH MEMORY INTERFACE 19-12 DEC R0 JP NZ，WR_BYTE ; Checks whether the end address for programmin

S3F84B8_UM_REV 1.00 19 EMBEDDED FLASH MEMORY INTERFACE 19-13 LD FMSECH,#06H ; Sets the base address of sector located in target address

S3F84B8_UM_REV 1.00 19 EMBEDDED FLASH MEMORY INTERFACE 19-14 19.1.8 READING The read operation starts using the ‘LDC’ instruction. Program Proc

S3F84B8_UM_REV 1.00 19 EMBEDDED FLASH MEMORY INTERFACE 19-15 19.1.9 HARD LOCK PROTECTION You can set Hard Lock Protection by writing ‘0110B’ in F

S3F84B8_UM_REV 1.00 20 LOW VOLTAGE RESET 20-1 20 LOW VOLTAGE RESET 20.1 OVERVIEW OF LOW VOLTAGE RESET Using the Smart option (3FH.7 in ROM), you

S3F84B8_UM_REV 1.00 20 LOW VOLTAGE RESET 20-2 +-VREFBGRVREFVIN VDDN.FnRESETWhen the VDD level is lowerthan VLVRComparatorNOTE: BGR is Band Gap r

S3F84B8_UM_REV 1.00 21 ELECTRICAL DATA 21-1 21 ELECTRICAL DATA 21.1 OVERVIEW OF ELECTRICAL DATA This section describes the electrical characteri

Revision History Revision No. Date Description Author(s) 0.00 Sep. 9, 2009  Initial draft Wei Ningning1.00 April. 30, 2010  Rele

S3F84B8_UM_REV 1.00 1 OVERVIEW OF S3F84B8 MICROCONTROLLER 1-13 Figure 1-9 shows the Pin Circuit Type 3 (P0.2) in S3F84B8. IN Figure 1-9

S3F84B8_UM_REV 1.00 21 ELECTRICAL DATA 21-2 Table 21-1 Absolute Maximum Ratings (TA = 25C) Parameter Symbol Conditions Rating Unit Suppl

S3F84B8_UM_REV 1.00 21 ELECTRICAL DATA 21-3 Table 21-2 DC Electrical Characteristics (TA = –40C to + 85C, VDD = 1.8V to 5.5V) Parameter Sy

S3F84B8_UM_REV 1.00 21 ELECTRICAL DATA 21-4 Parameter Symbol Conditions Minimum Typical Maximum UnitVDD = 4.5 to 5.5V (LVR enabled) TA = – 40C

S3F84B8_UM_REV 1.00 21 ELECTRICAL DATA 21-5 Table 21-4 Oscillator Characteristics (TA = –40C to + 85C) Oscillator Clock Circuit Test Conditi

S3F84B8_UM_REV 1.00 21 ELECTRICAL DATA 21-6 Table 21-5 Oscillation Stabilization Time (TA = –40°C to + 85°C, VDD = 1.8V to 5.5V) Oscillator

S3F84B8_UM_REV 1.00 21 ELECTRICAL DATA 21-7 10 MHzExternal Clock Frequency8 MHz1 MHz11.84567Supply Voltage (V)2 MHz3 MHz4 MHz..5.54.52.7400KHz2.0

S3F84B8_UM_REV 1.00 21 ELECTRICAL DATA 21-8 Table 21-6 Data Retention Supply Voltage in Stop Mode (TA = –40C to + 85C, VDD = 1.8V to 5.5V)

S3F84B8_UM_REV 1.00 21 ELECTRICAL DATA 21-9 Table 21-7 A/D Converter Electrical Characteristics (TA = –40C to + 85C, VDD = 1.8V to 5.5V,

S3F84B8_UM_REV 1.00 21 ELECTRICAL DATA 21-10 Table 21-8 OP AMP Electrical Characteristics (TA = –40C to + 85C, VDD = 2.0V to 5.5V) Paramete

S3F84B8_UM_REV 1.00 21 ELECTRICAL DATA 21-11 Table 21-10 LVR Circuit Characteristics (TA = 25C, VDD = 1.8V to 5.5V) Parameter Symbol Condit

S3F84B8_UM_REV 1.00 2 ADDRESS SPACES 2-1 2 ADDRESS SPACES 2.1 OVERVIEW OF ADDRESS SPACES The S3F84B8 microcontroller consists of two kinds of ad

S3F84B8_UM_REV 1.00 21 ELECTRICAL DATA 21-12 VSS VDD104S3F84B8NOTE: To have better EFT performance , It is recommended to1. Add a 104 capacitor

S3F84B8_UM_REV 1.00 22 DEVELOPMENT TOOLS 22-1 22 DEVELOPMENT TOOLS 22.1 OVERVIEW OF DEVELOPMENT TOOLS Samsung provides a powerful and easy-to-us

S3F84B8_UM_REV 1.00 22 DEVELOPMENT TOOLS 22-2 22.2 DEVELOPMENT SYSTEM CONFIGURATION Figure 22-1 shows the Development System Configuration. BusE

S3F84B8_UM_REV 1.00 22 DEVELOPMENT TOOLS 22-3 22.3 TB84B8 TARGET BOARD The TB84B8 target board is used for S3F84B8 microcontrollers. It is operat

S3F84B8_UM_REV 1.00 22 DEVELOPMENT TOOLS 22-4 Table 22-1 TB84B8 Components Mark Usage Description S1 100-cable interface Connect the emulator

S3F84B8_UM_REV 1.00 22 DEVELOPMENT TOOLS 22-5 Table 22-3 Using Single Header Pins to Select Clock Source and Enable/Disable PWM Target Board

S3F84B8_UM_REV 1.00 22 DEVELOPMENT TOOLS 22-6 ONOFFLowHigh (Default )NOTE:1. For EVA chip , smart option is determined by DIP switch not software.

S3F84B8_UM_REV 1.00 22 DEVELOPMENT TOOLS 22-7 (Top View )56S3C84T5S320-PIN DIP SOCKET24681013579VDDP2.7/ADC 7/(SCL )P2.6/ADC 6/(SDA )P2.5/ADC 5/CM

S3F84B8_UM_REV 1.00 22 DEVELOPMENT TOOLS 22-8 22.4 THIRD PARTIES FOR DEVELOPMENT TOOLS Samsung uses a complete line of development tools from thi

S3F84B8_UM_REV 1.00 22 DEVELOPMENT TOOLS 22-9 22.4.1 OTP/MTP PROGRAMMER (WRITER) SPW-uni Single OTP/MTP/Flash Programmer  Supports Download/Up

S3F84B8_UM_REV 1.00 2 ADDRESS SPACES 2-2 2.2 INTERNAL PROGRAM MEMORY (ROM) The internal program memory (ROM) stores program codes or table data.

S3F84B8_UM_REV 1.00 22 DEVELOPMENT TOOLS 22-10 (Windows 95/98/2000/XP)  Supports full functions of OTP/MTP programmer (Read, Program, Verify, Bla

S3F84B8_UM_REV 1.00 23 MECHANICAL DATA 23-1 23 MECHANICAL DATA 23.1 OVERVIEW OF MECHANICAL DATA S3F84B8 is available in a 20-pin DIP package (Sa

S3F84B8_UM_REV 1.00 23 MECHANICAL DATA 23-2 NOTE: Dimensions are in millimeters.20-SOP-37510.300.30#11#20#1#1013.14 MAX12.740.20(0.66)0-8

S3F84B8_UM_REV 1.00 2 ADDRESS SPACES 2-3 2.2.1 SMART OPTION NOTE:1. The unused bits of 3CH, 3DH, 3EH, 3FH must be logic "1".2. When LV

S3F84B8_UM_REV 1.00 2 ADDRESS SPACES 2-4 2.3 REGISTER ARCHITECTURE In the S3F84B8 microcontroller implementation, the upper 64 byte area of regis

S3F84B8_UM_REV 1.00 2 ADDRESS SPACES 2-5 System Registers(Register Addressing Mode)General Purpose Register(Register Addressing Mode)Bank 1System

S3F84B8_UM_REV 1.00 2 ADDRESS SPACES 2-6 2.3.1 REGISTER PAGE POINTER (PP) The S3F8 series architecture supports the logical expansion of physical

S3F84B8_UM_REV 1.00 2 ADDRESS SPACES 2-7 2.3.1.1 Register Set 1 The term set 1 refers to the upper 64 bytes of register file in locations C0H–FFH

S3F84B8_UM_REV 1.00 2 ADDRESS SPACES 2-8 2.3.1.3 Prime Register Space The lower 192 bytes (00H–BFH) of 256 byte register page 0 in S3F84B8 is cal

S3F84B8_UM_REV 1.00 2 ADDRESS SPACES 2-9 2.3.1.4 Working Registers Instructions can access specific 8-bit registers or 16-bit register pairs usin

Table of Contents 1 OVERVIEW OF S3F84B8 MICROCONTROLLER...1-1 1.1 S3C8-Series Microcontrollers ...

S3F84B8_UM_REV 1.00 2 ADDRESS SPACES 2-10 2.3.2 USING THE REGISTER POINTS (RP) Register pointers RP0 and RP1, mapped to addresses D6H and D7H in

S3F84B8_UM_REV 1.00 2 ADDRESS SPACES 2-11 16-ByteContiguousworkingRegister blockRegister FileContains 328-Byte Slices0 0 0 0 0 X X XRP11

S3F84B8_UM_REV 1.00 2 ADDRESS SPACES 2-12 2.4 REGISTER ADDRESSING The S3C8 series register architecture provides an efficient method of working r

S3F84B8_UM_REV 1.00 2 ADDRESS SPACES 2-13 RP1RP0RegisterPointers00HAllAddressingModesPage 0Indirect Register,IndexedAddressingModesPage 0Register

S3F84B8_UM_REV 1.00 2 ADDRESS SPACES 2-14 2.4.1 COMMON WORKING REGISTER AREA (C0H–CFH) After a reset, register pointers RP0 and RP1 automatically

S3F84B8_UM_REV 1.00 2 ADDRESS SPACES 2-15 2.4.2 4-BIT WORKING REGISTER ADDRESSING Each register pointer defines a movable 8 byte slice of working

S3F84B8_UM_REV 1.00 2 ADDRESS SPACES 2-16 Registeraddress(76H)RP00 1 1 1 0 0 0 00 1 1 1 0 1 1 0R60 1 1 0 1 1 1 0Selects RP0Instr

S3F84B8_UM_REV 1.00 2 ADDRESS SPACES 2-17 2.4.3 8-BIT WORKING REGISTER ADDRESSING You can also use 8-bit working register addressing to access re

S3F84B8_UM_REV 1.00 2 ADDRESS SPACES 2-18 8-bit addressform instruction'LD R11, R2'RP00 1 1 0 0 0 0 01 1 0 0 1 0 1 1Sel

S3F84B8_UM_REV 1.00 2 ADDRESS SPACES 2-19 2.4.4 SYSTEM AND USER STACK The S3C8 series microcontrollers use the system stack for data storage, sub

4.1 Overview of Control Registers ...

S3F84B8_UM_REV 1.00 2 ADDRESS SPACES 2-20 Example 2-4 Standard Stack Operations Using PUSH and POP Following example shows you how to perform

S3F84B8_UM_REV 1.00 3 ADDRESSING MODES 3-1 3 ADDRESSING MODES 3.1 OVERVIEW OF ADDRESSING MODES The program counter fetches the instructions stor

S3F84B8_UM_REV 1.00 3 ADDRESSING MODES 3-2 3.2 REGISTER (R) ADDRESSING MODE In Register (R) addressing mode, the operand value is the content of

S3F84B8_UM_REV 1.00 3 ADDRESSING MODES 3-3 3.3 INDIRECT REGISTER (IR) ADDRESSING MODE In Indirect Register (IR) addressing mode, the content of a

S3F84B8_UM_REV 1.00 3 ADDRESSING MODES 3-4 3.4 INDIRECT REGISTER (IR) ADDRESSING MODE (CONTINUED) dstOPCODEPAIRPoints toRegister PairExampleInstr

S3F84B8_UM_REV 1.00 3 ADDRESSING MODES 3-5 3.5 INDIRECT REGISTER (IR) ADDRESSING MODE (CONTINUED) dstOPCODEADDRESS4-bitWorkingRegisterAddressPoin

S3F84B8_UM_REV 1.00 3 ADDRESSING MODES 3-6 3.6 INDIRECT REGISTER (IR) ADDRESSING MODE (CONCLUDED) dstOPCODE4-bit WorkingRegister AddressSample In

S3F84B8_UM_REV 1.00 3 ADDRESSING MODES 3-7 3.7 INDEXED (X) ADDRESSING MODE Indexed (X) addressing mode adds an offset value to base address while

S3F84B8_UM_REV 1.00 3 ADDRESSING MODES 3-8 3.8 INDEXED (X) ADDRESSING MODE (CONTINUED) Register FileOPERANDProgram MemoryorData MemoryPoint to Wo

S3F84B8_UM_REV 1.00 3 ADDRESSING MODES 3-9 3.9 INDEXED (X) ADDRESSING MODE (CONCLUDED) Register FileOPERANDProgram MemoryorData MemoryPoint to Wo

5.1.5 S3F84B8 Interrupt Structure...

S3F84B8_UM_REV 1.00 3 ADDRESSING MODES 3-10 3.10 DIRECT ADDRESS (DA) MODE In Direct Address (DA) mode, the instruction provides an operand’s 16-b

S3F84B8_UM_REV 1.00 3 ADDRESSING MODES 3-11 3.11 DIRECT ADDRESS (DA) MODE (CONTINUED) OPCODEProgram MemoryLower Address ByteMemoryAddressUsedUppe

S3F84B8_UM_REV 1.00 3 ADDRESSING MODES 3-12 3.12 INDIRECT ADDRESS (IA) MODE In Indirect Address (IA) mode, the instruction specifies an address l

S3F84B8_UM_REV 1.00 3 ADDRESSING MODES 3-13 3.13 RELATIVE ADDRESS (RA) MODE In Relative Address (RA) mode, a two’s complement signed displacement

S3F84B8_UM_REV 1.00 3 ADDRESSING MODES 3-14 3.14 IMMEDIATE MODE (IM) In Immediate (IM) addressing mode, the operand value used in instruction is

S3F84B8_UM_REV 1.00 4 CONTROL REGISTERS 4-1 4 CONTROL REGISTERS 4.1 OVERVIEW OF CONTROL REGISTERS This section provides a detailed description o

S3F84B8_UM_REV 1.00 4 CONTROL REGISTERS 4-2 Address and Location RESET Value (Bit) Register Name Mnemonic Address R/W 7 6 5 4 3 2 1 0Port 0 c

S3F84B8_UM_REV 1.00 4 CONTROL REGISTERS 4-3 Table 4-2 System and Peripheral Control Registers Set1 Bank1 Address and Location RESET Value (Bi

S3F84B8_UM_REV 1.00 4 CONTROL REGISTERS 4-4 FLAGS - System Flags Register.7.6.5Bit IdentifierRESET ValueRead/WriteR = Read-onlyW = Write-onlyR/W =

S3F84B8_UM_REV 1.00 4 CONTROL REGISTERS 4-5 4.1.1 ADCON — A/D CONVERTER CONTROL REGISTER: FAH, BANK0 Bit Identifier .7 .6 .5 .4 .3 .2 .1

6.3.17 CP — Compare ...

S3F84B8_UM_REV 1.00 4 CONTROL REGISTERS 4-6 4.1.2 AMTDATA — ANTI-MIS-TRIGGER DATA REGISTER: F6H, BANK0 Bit Identifier .7 .6 .5 .4 .3 .2 .1

S3F84B8_UM_REV 1.00 4 CONTROL REGISTERS 4-7 4.1.4 BUZCON — BUZ CONTROL REGISTER: F7H, BANK0 Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 RESET

S3F84B8_UM_REV 1.00 4 CONTROL REGISTERS 4-8 4.1.5 CLKCON — CLOCK CONTROL REGISTER: D4H, BANK0 Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 RESE

S3F84B8_UM_REV 1.00 4 CONTROL REGISTERS 4-9 4.1.6 CMP0CON — COMPARATOR0 CONTROL REGISTER: EAH, BANK0 Bit Identifier .7 .6 .5 .4 .3 .2 .1

S3F84B8_UM_REV 1.00 4 CONTROL REGISTERS 4-10 4.1.7 CMP1CON — COMPARATOR1 CONTROL REGISTER: EBH, BANK0 Bit Identifier .7 .6 .5 .4 .3 .2 .1

S3F84B8_UM_REV 1.00 4 CONTROL REGISTERS 4-11 4.1.8 CMP2CON — COMPARATOR1 CONTROL REGISTER: ECH, BANK0 Bit Identifier .7 .6 .5 .4 .3 .2 .1

S3F84B8_UM_REV 1.00 4 CONTROL REGISTERS 4-12 4.1.9 CMP3CON — COMPARATOR1 CONTROL REGISTER: EDH, BANK0 Bit Identifier .7 .6 .5 .4 .3 .2 .1

S3F84B8_UM_REV 1.00 4 CONTROL REGISTERS 4-13 4.1.10 CMPINT — COMPARATOR INTERRUPT MODE CONTROL REGISTER: EEH, BANK0 Bit Identifier .7 .6 .5

S3F84B8_UM_REV 1.00 4 CONTROL REGISTERS 4-14 4.1.11 FLAGS — SYSTEM FLAGS REGISTER: D5H, BANK0 Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 Rese

S3F84B8_UM_REV 1.00 4 CONTROL REGISTERS 4-15 4.1.12 FMCON — FLASH MEMORY CONTROL REGISTER: F5H, BANK1 Bit Identifier .7 .6 .5 .4 .3 .2 .1

6.3.70 TCM — Test Complement Under Mask ... 6-82 6.3.71

S3F84B8_UM_REV 1.00 4 CONTROL REGISTERS 4-16 4.1.14 FMSECL — FLASH MEMORY SECTOR ADDRESS REGISTER (LOW BYTE): F8H, BANK1 Bit Identifier .7 .6

S3F84B8_UM_REV 1.00 4 CONTROL REGISTERS 4-17 4.1.16 IMR — INTERRUPT MASK REGISTER: DDH, BANK0 Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 Rese

S3F84B8_UM_REV 1.00 4 CONTROL REGISTERS 4-18 4.1.17 IPH — INSTRUCTION POINTER (HIGH BYTE): DAH, BANK0 Bit Identifier .7 .6 .5 .4 .3 .2 .1

S3F84B8_UM_REV 1.00 4 CONTROL REGISTERS 4-19 4.1.19 IPR — INTERRUPT PRIORITY REGISTER: FFH, BANK0 Bit Identifier .7 .6 .5 .4 .3 .2 .1 .

S3F84B8_UM_REV 1.00 4 CONTROL REGISTERS 4-20 4.1.20 IRQ — INTERRUPT REQUEST REGISTER: DCH, BANK0 Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 R

S3F84B8_UM_REV 1.00 4 CONTROL REGISTERS 4-21 4.1.21 OPACON — OP AMP CONTROL REGISTER: E0H, BANK1 Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 R

S3F84B8_UM_REV 1.00 4 CONTROL REGISTERS 4-22 4.1.22 P0CONH — PORT 0 CONTROL REGISTER (HIGH BYTE): E4H, BANK0 Bit Identifier .7 .6 .5 .4 .3

S3F84B8_UM_REV 1.00 4 CONTROL REGISTERS 4-23 4.1.23 P0CONL — PORT 0 CONTROL REGISTER (LOW BYTE): E5H, BANK0 Bit Identifier .7 .6 .5 .4 .3 .

S3F84B8_UM_REV 1.00 4 CONTROL REGISTERS 4-24 4.1.24 P0INT — PORT 0 INTERRUPT CONTROL REGISTER: E3H, BANK0 Bit Identifier .7 .6 .

S3F84B8_UM_REV 1.00 4 CONTROL REGISTERS 4-25 4.1.25 P0PND — PORT 0 INTERRUPT PENDING REGISTER: E6H, BANK0 Bit Identifier .7 .6 .5 .4 .3 .2

12.1.2.2 Timer 0 Control Register (TCCON)... 12-2 12.1.3 B

S3F84B8_UM_REV 1.00 4 CONTROL REGISTERS 4-26 4.1.26 P1CON — PORT 1 CONTROL REGISTER: E7H, BANK0 Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 RE

S3F84B8_UM_REV 1.00 4 CONTROL REGISTERS 4-27 4.1.27 P2CONH — PORT 2 CONTROL REGISTER (HIGH BYTE): E8H, BANK0 Bit Identifier .7 .6 .5 .4 .3

S3F84B8_UM_REV 1.00 4 CONTROL REGISTERS 4-28 4.1.28 P2CONL — PORT 2 CONTROL REGISTER (LOW BYTE): E9H, BANK0 Bit Identifier .7 .6 .5 .4 .3 .

S3F84B8_UM_REV 1.00 4 CONTROL REGISTERS 4-29 4.1.29 PWMCON — PWM CONTROL REGISTER: EFH, BANK0 Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 RESE

S3F84B8_UM_REV 1.00 4 CONTROL REGISTERS 4-30 4.1.30 PWMCCON — PWM CMP CONTROL REGISTER: F0H, BANK0 Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0

S3F84B8_UM_REV 1.00 4 CONTROL REGISTERS 4-31 4.1.31 PWMDL — COMPARATOR0 OUTPUT DELAY REGISTER: F5H, BANK0 Bit Identifier .7 .6 .5 .4 .3 .2

S3F84B8_UM_REV 1.00 4 CONTROL REGISTERS 4-32 4.1.33 RESETID — RESET SOURCE INDICATING REGISTER: F2H, BANK1 Bit Identifier .7 .6 .5 .4 .3 .2

S3F84B8_UM_REV 1.00 4 CONTROL REGISTERS 4-33 4.1.34 RP0 — REGISTER POINTER 0: D6H, BANK0 Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 Reset Val

S3F84B8_UM_REV 1.00 4 CONTROL REGISTERS 4-34 4.1.36 SPL — STACK POINTER: D9H, BANK0 Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 Reset Value x

S3F84B8_UM_REV 1.00 4 CONTROL REGISTERS 4-35 4.1.38 SYM — SYSTEM MODE REGISTER: DEH, BANK0 Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 Reset V