Samsung S3F84B8 User Manual

S3F84B8 USER’S MANUAL V1.0 PRODUCT OVERVIEW 1-1 1 PRODUCT OVERVIEW S3C8-SERIES MICROCONTROLLERS Samsung's SAM8RC family of 8-bit single-chi

PRODUCT OVERVIEW S3F84B8 USER'S MANUAL V1.0 1-10 Figure 1-9. Pin Circuit Type 3 (P0.2) VDDI/OOutput Disable(input mode)DataXinPull-up en

INTERRUPT STRUCTURE S3F84B8 USER’S MANUAL V1.0 5-10 INTERRUPT PRIORITY REGISTER (IPR) The interrupt priority register, IPR (FFH, Set1, Bank0), i

S3F84B8 USER’S MANUAL V1.0 INTERRUPT STRUCTURE 5-11 Interrupt Priority Register (IPR)FFH, Set1, Bank0, R/W.7 .6 .5 .4 .3 .2 .1 .0MSB LSBGroup A0

INTERRUPT STRUCTURE S3F84B8 USER’S MANUAL V1.0 5-12 INTERRUPT REQUEST REGISTER (IRQ) You can poll bit values in the interrupt request register,

S3F84B8 USER’S MANUAL V1.0 INTERRUPT STRUCTURE 5-13 INTERRUPT PENDING FUNCTION TYPES Overview There are two types of interrupt pending bits: one

INTERRUPT STRUCTURE S3F84B8 USER’S MANUAL V1.0 5-14 INTERRUPT SOURCE POLLING SEQUENCE The interrupt request polling and servicing sequence is as

S3F84B8 USER’S MANUAL V1.0 INTERRUPT STRUCTURE 5-15 GENERATING INTERRUPT VECTOR ADDRESSES The interrupt vector area in the ROM (00H–FFH) contain

INTERRUPT STRUCTURE S3F84B8 USER’S MANUAL V1.0 5-16 FAST INTERRUPT PROCESSING (Continued) Two other system registers support fast interrupt proc

S3F84B8 USER’S MANUAL V1.0 INTERRUPT STRUCTURE 5-17 NOTES

S3F84B8 USER’S MANUAL V1.0 INSTRUCTION SET 6-1 6 INSTRUCTION SET OVERVIEW The SAM8RC instruction set is specifically designed to support the la

INSTRUCTION SET S3F84B8 USER’S MANUAL V1.0 6-2 Table 6-1. Instruction Group Summary Mnemonic Operands Instru

S3F84B8 USER’S MANUAL V1.0 ADDRESS SPACES 2-1 2 ADDRESS SPACES OVERVIEW The S3F84B8 microcontroller has two kinds of address space: — Internal

S3F84B8 USER’S MANUAL V1.0 INSTRUCTION SET 6-3 Table 6-1. Instruction Group Summary (Continued) Mnemonic Operands Instruction Arithmetic Inst

INSTRUCTION SET S3F84B8 USER’S MANUAL V1.0 6-4 Table 6-1. Instruction Group Summary (Continued) Mnemonic Oper

S3F84B8 USER’S MANUAL V1.0 INSTRUCTION SET 6-5 Table 6-1. Instruction Group Summary (Concluded) Mnemonic Operands Instruction Rotate and Shif

INSTRUCTION SET S3F84B8 USER’S MANUAL V1.0 6-6 FLAGS REGISTER (FLAGS) The flags register FLAGS contains eight

S3F84B8 USER’S MANUAL V1.0 INSTRUCTION SET 6-7 FLAG DESCRIPTIONS C Carry Flag (FLAGS.7) The C flag is set to "1" if the result from

INSTRUCTION SET S3F84B8 USER’S MANUAL V1.0 6-8 INSTRUCTION SET NOTATION Table 6-2. Flag Notation Conventions

S3F84B8 USER’S MANUAL V1.0 INSTRUCTION SET 6-9 Table 6-4. Instruction Notation Conventions Notation Description Actual Operand Range cc Cond

INSTRUCTION SET S3F84B8 USER’S MANUAL V1.0 6-10 Table 6-5. Opcode Quick Reference OPCODE MAP LOWER NIBBLE (H

S3F84B8 USER’S MANUAL V1.0 INSTRUCTION SET 6-11 Table 6-5. Opcode Quick Reference (Continued) OPCODE MAP LOWER NIBBLE (HEX) – 8 9 A B C D E F

INSTRUCTION SET S3F84B8 USER’S MANUAL V1.0 6-12 CONDITION CODES The opcode of a conditional jump always conta

ADDRESS SPACES S3F84B8 USER’S MANUAL V1.0 2-2 PROGRAM MEMORY (ROM) Program memory (ROM) stores program codes or table data. The S3F84B8 have 8Kb

S3F84B8 USER’S MANUAL V1.0 INSTRUCTION SET 6-13 INSTRUCTION DESCRIPTIONS This section contains detailed information and programming examples fo

S3F84B8 USER’S MANUAL V1.0 INSTRUCTION SET 6-1 ADC — Add with carry ADC dst,src Operation: dst ← dst + src + c The source operand, al

INSTRUCTION SET S3F84B8 USER’S MANUAL V1.0 6-2 ADD — Add ADD dst,src Operation: dst ← dst + src The sou

S3F84B8 USER’S MANUAL V1.0 INSTRUCTION SET 6-3 AND — Logical AND AND dst,src Operation: dst ← dst AND src The source operand is logical

INSTRUCTION SET S3F84B8 USER’S MANUAL V1.0 6-4 BAND — Bit AND BAND dst,src.b BAND dst.b,src Operation: dst(

S3F84B8 USER’S MANUAL V1.0 INSTRUCTION SET 6-5 BCP — Bit Compare BCP dst,src.b Operation: dst(0) – src(b) The specified bit of the source i

INSTRUCTION SET S3F84B8 USER’S MANUAL V1.0 6-6 BITC — Bit Complement BITC dst.b Operation: dst(b) ← NOT dst

S3F84B8 USER’S MANUAL V1.0 INSTRUCTION SET 6-7 BITR — Bit Reset BITR dst.b Operation: dst(b) ← 0 The BITR instruction clears the specified b

INSTRUCTION SET S3F84B8 USER’S MANUAL V1.0 6-8 BITS — Bit Set BITS dst.b Operation: dst(b) ← 1 The BITS

S3F84B8 USER’S MANUAL V1.0 ADDRESS SPACES 2-3 Smart Option NOTES:1. The unused bits of 3CH, 3DH, 3EH, 3FH must be logic "1".2. Whe

S3F84B8 USER’S MANUAL V1.0 INSTRUCTION SET 6-9 BOR — Bit OR BOR dst,src.b BOR dst.b,src Operation: dst(0) ← dst(0) OR src(b) or dst(b)

INSTRUCTION SET S3F84B8 USER’S MANUAL V1.0 6-10 BTJRF — Bit Test, Jump Relative on False BTJRF dst,src.b Ope

S3F84B8 USER’S MANUAL V1.0 INSTRUCTION SET 6-11 BTJRT — Bit Test, Jump Relative on True BTJRT dst,src.b Operation: If src(b) is a "1&quo

INSTRUCTION SET S3F84B8 USER’S MANUAL V1.0 6-12 BXOR — Bit XOR BXOR dst,src.b BXOR dst.b,src Operation: dst

S3F84B8 USER’S MANUAL V1.0 INSTRUCTION SET 6-13 CALL — Call Procedure CALL dst Operation: SP ← SP – 1 @SP ← PCL SP ← SP –1 @SP ← PCH PC ←

INSTRUCTION SET S3F84B8 USER’S MANUAL V1.0 6-14 CCF — Complement Carry Flag CCF Operation: C ← NOT C The c

S3F84B8 USER’S MANUAL V1.0 INSTRUCTION SET 6-15 CLR — Clear CLR dst Operation: dst ← "0" The destination location is cleared to &q

INSTRUCTION SET S3F84B8 USER’S MANUAL V1.0 6-16 COM — Complement COM dst Operation: dst ← NOT dst The c

S3F84B8 USER’S MANUAL V1.0 INSTRUCTION SET 6-17 CP — Compare CP dst,src Operation: dst – src The source operand is compared to (subtracted

INSTRUCTION SET S3F84B8 USER’S MANUAL V1.0 6-18 CPIJE — Compare, Increment, and Jump on Equal CPIJE dst,src,

ADDRESS SPACES S3F84B8 USER’S MANUAL V1.0 2-4 REGISTER ARCHITECTURE In the S3F84B8 implementation, the upper 64-byte area of register files is e

S3F84B8 USER’S MANUAL V1.0 INSTRUCTION SET 6-19 CPIJNE — Compare, Increment, and Jump on Non-Equal CPIJNE dst,src,RA Operation: If dst – src

INSTRUCTION SET S3F84B8 USER’S MANUAL V1.0 6-20 DA — Decimal Adjust DA dst Operation: dst ← DA dst The de

S3F84B8 USER’S MANUAL V1.0 INSTRUCTION SET 6-21 DA — Decimal Adjust DA (Continued) Example: Given: Working register R0 contains the value 15

INSTRUCTION SET S3F84B8 USER’S MANUAL V1.0 6-22 DEC — Decrement DEC dst Operation: dst ← dst – 1 The conte

S3F84B8 USER’S MANUAL V1.0 INSTRUCTION SET 6-23 DECW — Decrement Word DECW dst Operation: dst ← dst – 1 The contents of the destination lo

INSTRUCTION SET S3F84B8 USER’S MANUAL V1.0 6-24 DI — Disable Interrupts DI Operation: SYM (0) ← 0 Bit zero

S3F84B8 USER’S MANUAL V1.0 INSTRUCTION SET 6-25 DIV — Divide (Unsigned) DIV dst,src Operation: dst ÷ src dst (UPPER) ← REMAINDER dst

INSTRUCTION SET S3F84B8 USER’S MANUAL V1.0 6-26 DJNZ — Decrement and Jump if Non-Zero DJNZ r,dst Operation:

S3F84B8 USER’S MANUAL V1.0 INSTRUCTION SET 6-27 EI — Enable Interrupts EI Operation: SYM (0) ← 1 An EI instruction sets bit zero of the sy

INSTRUCTION SET S3F84B8 USER’S MANUAL V1.0 6-28 ENTER — Enter ENTER Operation: SP ← SP – 2 @SP ← IP IP ← P

S3F84B8 USER’S MANUAL V1.0 ADDRESS SPACES 2-5 System Registers(Register Addressing Mode)General Purpose Register(Register Addressing Mode)Bank 1

S3F84B8 USER’S MANUAL V1.0 INSTRUCTION SET 6-29 EXIT — Exit EXIT Operation: IP ← @SP SP ← SP + 2 PC ← @IP IP ← IP + 2 This instruct

INSTRUCTION SET S3F84B8 USER’S MANUAL V1.0 6-30 IDLE — Idle Operation IDLE Operation: The IDLE instructi

S3F84B8 USER’S MANUAL V1.0 INSTRUCTION SET 6-31 INC — Increment INC dst Operation: dst ← dst + 1 The contents of the destination operand a

INSTRUCTION SET S3F84B8 USER’S MANUAL V1.0 6-32 INCW — Increment Word INCW dst Operation: dst ← dst + 1

S3F84B8 USER’S MANUAL V1.0 INSTRUCTION SET 6-33 IRET — Interrupt Return IRET IRET (Normal) IRET (Fast) Operation: FLAGS ← @SP PC ↔ IP S

INSTRUCTION SET S3F84B8 USER’S MANUAL V1.0 6-34 JP — Jump JP cc,dst (Conditional) JP dst (Unconditional)

S3F84B8 USER’S MANUAL V1.0 INSTRUCTION SET 6-35 JR — Jump Relative JR cc,dst Operation: If cc is true, PC ← PC + dst If the condition

INSTRUCTION SET S3F84B8 USER’S MANUAL V1.0 6-36 LD — Load LD dst,src Operation: dst ← src The contents of

S3F84B8 USER’S MANUAL V1.0 INSTRUCTION SET 6-37 LD — Load LD (Continued) Examples: Given: R0 = 01H, R1 = 0AH, register 00H = 01H, regi

INSTRUCTION SET S3F84B8 USER’S MANUAL V1.0 6-38 LDB — Load Bit LDB dst,src.b LDB dst.b,src Operation: dst(0

ADDRESS SPACES S3F84B8 USER’S MANUAL V1.0 2-6 Register Page Pointer (PP)DFH, Set 1, R/WLSBMSB .7 .6 .5 .4 .3 .2 .1 .0Destination register page s

S3F84B8 USER’S MANUAL V1.0 INSTRUCTION SET 6-39 LDC/LDE — Load Memory LDC/LDE dst,src Operation: dst ← src This instruction loads a byte fro

INSTRUCTION SET S3F84B8 USER’S MANUAL V1.0 6-40 LDC/LDE — Load Memory LDC/LDE (Continued) Examples: Given:

S3F84B8 USER’S MANUAL V1.0 INSTRUCTION SET 6-41 LDCD/LDED — Load Memory and Decrement LDCD/LDED dst,src Operation: dst ← src rr ← rr – 1

INSTRUCTION SET S3F84B8 USER’S MANUAL V1.0 6-42 LDCI/LDEI — Load Memory and Increment LDCI/LDEI dst,src Oper

S3F84B8 USER’S MANUAL V1.0 INSTRUCTION SET 6-43 LDCPD/LDEPD — Load Memory with Pre-Decrement LDCPD/ LDEPD dst,src Operation: rr ← rr – 1

INSTRUCTION SET S3F84B8 USER’S MANUAL V1.0 6-44 LDCPI/LDEPI — Load Memory with Pre-Increment LDCPI/ LDEPI ds

S3F84B8 USER’S MANUAL V1.0 INSTRUCTION SET 6-45 LDW — Load Word LDW dst,src Operation: dst ← src The contents of the source (a word) are loa

INSTRUCTION SET S3F84B8 USER’S MANUAL V1.0 6-46 MULT — Multiply (Unsigned) MULT dst,src Operation: dst ← d

S3F84B8 USER’S MANUAL V1.0 INSTRUCTION SET 6-47 NEXT — Next NEXT Operation: PC ← @ IP IP ← IP + 2 The NEXT instruction is useful when

INSTRUCTION SET S3F84B8 USER’S MANUAL V1.0 6-48 NOP — No Operation NOP Operation: No action is performed whe

S3F84B8 USER’S MANUAL V1.0 ADDRESS SPACES 2-7 REGISTER SET 1 The term set 1 refers to the upper 64 bytes of the register file, locations C0H–FF

S3F84B8 USER’S MANUAL V1.0 INSTRUCTION SET 6-49 OR — Logical OR OR dst,src Operation: dst ← dst OR src The source operand is logically O

INSTRUCTION SET S3F84B8 USER’S MANUAL V1.0 6-50 POP — Pop From Stack POP dst Operation: dst ← @SP SP ←

S3F84B8 USER’S MANUAL V1.0 INSTRUCTION SET 6-51 POPUD — Pop User Stack (Decrementing) POPUD dst,src Operation: dst ← src IR ← IR – 1 Th

INSTRUCTION SET S3F84B8 USER’S MANUAL V1.0 6-52 POPUI — Pop User Stack (Incrementing) POPUI dst,src Operatio

S3F84B8 USER’S MANUAL V1.0 INSTRUCTION SET 6-53 PUSH — Push To Stack PUSH src Operation: SP ← SP – 1 @SP ← src A PUSH instruction dec

INSTRUCTION SET S3F84B8 USER’S MANUAL V1.0 6-54 PUSHUD — Push User Stack (Decrementing) PUSHUD dst,src Opera

S3F84B8 USER’S MANUAL V1.0 INSTRUCTION SET 6-55 PUSHUI — Push User Stack (Incrementing) PUSHUI dst,src Operation: IR ← IR + 1 dst ← src

INSTRUCTION SET S3F84B8 USER’S MANUAL V1.0 6-56 RCF — Reset Carry Flag RCF RCF Operation: C ← 0 The carr

S3F84B8 USER’S MANUAL V1.0 INSTRUCTION SET 6-57 RET — Return RET Operation: PC ← @SP SP ← SP + 2 The RET instruction is normally used

INSTRUCTION SET S3F84B8 USER’S MANUAL V1.0 6-58 RL — Rotate Left RL dst Operation: C ← dst (7) dst (0) ←

ADDRESS SPACES S3F84B8 USER’S MANUAL V1.0 2-8 PRIME REGISTER SPACE The lower 192 bytes (00H–BFH) of the S3F84B8's 256-byte register page 0

S3F84B8 USER’S MANUAL V1.0 INSTRUCTION SET 6-59 RLC — Rotate Left Through Carry RLC dst Operation: dst (0) ← C C ← dst (7) dst (n + 1

INSTRUCTION SET S3F84B8 USER’S MANUAL V1.0 6-60 RR — Rotate Right RR dst Operation: C ← dst (0) dst (7)

S3F84B8 USER’S MANUAL V1.0 INSTRUCTION SET 6-61 RRC — Rotate Right Through Carry RRC dst Operation: dst (7) ← C C ← dst (0) dst (n) ←

INSTRUCTION SET S3F84B8 USER’S MANUAL V1.0 6-62 SB0 — Select Bank 0 SB0 Operation: BANK ← 0 The SB0 instr

S3F84B8 USER’S MANUAL V1.0 INSTRUCTION SET 6-63 SB1 — Select Bank 1 SB1 Operation: BANK ← 1 The SB1 instruction sets the bank address flag

INSTRUCTION SET S3F84B8 USER’S MANUAL V1.0 6-64 SBC — Subtract with Carry SBC dst,src Operation: dst ← dst

S3F84B8 USER’S MANUAL V1.0 INSTRUCTION SET 6-65 SCF — Set Carry Flag SCF Operation: C ← 1 The carry flag (C) is set to logic one, regardles

INSTRUCTION SET S3F84B8 USER’S MANUAL V1.0 6-66 SRA — Shift Right Arithmetic SRA dst Operation: dst (7) ←

S3F84B8 USER’S MANUAL V1.0 INSTRUCTION SET 6-67 SRP/SRP0/SRP1 — Set Register Pointer SRP src SRP0 src SRP1 src Operation: If src (1) = 1

INSTRUCTION SET S3F84B8 USER’S MANUAL V1.0 6-68 STOP — Stop Operation STOP Operation: The STOP instruction

S3F84B8 USER’S MANUAL V1.0 ADDRESS SPACES 2-9 WORKING REGISTERS Instructions can access specific 8-bit registers or 16-bit register pairs using

S3F84B8 USER’S MANUAL V1.0 INSTRUCTION SET 6-69 SUB — Subtract SUB dst,src Operation: dst ← dst – src The source operand is subtracted fr

INSTRUCTION SET S3F84B8 USER’S MANUAL V1.0 6-70 SWAP — Swap Nibbles SWAP dst Operation: dst (0 – 3) ↔ d

S3F84B8 USER’S MANUAL V1.0 INSTRUCTION SET 6-71 TCM — Test Complement Under Mask TCM dst,src Operation: (NOT dst) AND src This instructio

INSTRUCTION SET S3F84B8 USER’S MANUAL V1.0 6-72 TM — Test Under Mask TM dst,src Operation: dst AND src

S3F84B8 USER’S MANUAL V1.0 INSTRUCTION SET 6-73 WFI — Wait for Interrupt WFI Operation: The CPU is effectively halted until an interrupt occu

INSTRUCTION SET S3F84B8 USER’S MANUAL V1.0 6-74 XOR — Logical Exclusive OR XOR dst,src Operation: dst ← ds

S3F84B8 USER’S MANUAL V1.0 INSTRUCTION SET 6-75 NOTES

S3F84B8 USER’S MANUAL V1.0 CLOCK CIRCUIT 7-1 7 CLOCK CIRCUIT OVERVIEW By smart option (3FH.1 – .0 in ROM), user can select internal RC oscillato

CLOCK CIRCUIT S3F84B8 USER’S MANUAL V1.0 7-2 CLOCK STATUS DURING POWER-DOWN MODES The

S3F84B8 PRELIMINARY SPEC V0.4 CLOCK CIRCUIT 7-3 MUXSelected OSCNoiseFilterOscillatorWake-upOscillatorStopCLKCON.7INT Pin CLKCON.4-.31/21/16MUXSto

PRODUCT OVERVIEW S3F84B8 USER’S MANUAL V1.0 1-2 FEATURES CPU • SAM8RC CPU core Memory • 8K-byte internal multi time program memory Full-Flash

ADDRESS SPACES S3F84B8 USER’S MANUAL V1.0 2-10 USING THE REGISTER POINTS Register pointers RP0 and RP1, mapped to addresses D6H and D7H in set 1

CLOCK CIRCUIT S3F84B8 USER’S MANUAL V1.0 7-4 NOTES

S3F84B8 USER’S MANUAL V1.0 RESET AND POWER-DOWN 8-1 8 RESET and POWER-DOWN SYSTEM RESET OVERVIEW By smart option (3FH.7 in ROM), user can sele

RESET AND POWER-DOWN S3F84B8 USER’S MANUAL V1.0 8-2 +-VREFBGR VDDVREFVIN VDDN.FInternal SystemRESETBWhen the VDD levelis lower than VLVR Compara

S3F84B8 USER’S MANUAL V1.0 RESET AND POWER-DOWN 8-3 MCU Initialization Sequence The following sequence of events occurs during a Reset operatio

RESET AND POWER-DOWN S3F84B8 USER’S MANUAL V1.0 8-4 POWER-DOWN MODES STOP MODE Stop mode is invoked by the instruction STOP (opcode 7FH). In Sto

S3F84B8 USER’S MANUAL V1.0 RESET AND POWER-DOWN 8-5 will be increased significantly.

RESET AND POWER-DOWN S3F84B8 USER’S MANUAL V1.0 8-6 HARDWARE RESET VALUES The reset values for CPU and system registers, peripheral control regi

S3F84B8 USER’S MANUAL V1.0 RESET AND POWER-DOWN 8-7 Table 8-1. System and Peripheral Control Registers Set1 Bank 0(Continued) Register Name Mn

RESET AND POWER-DOWN S3F84B8 USER’S MANUAL V1.0 8-8 Table 8-1. System and Peripheral Control Registers Set1 Bank1 Register name Mnemonic Addre

S3F84B8 USER’S MANUAL V1.0 RESET AND POWER-DOWN 8-9 NOTES

S3F84B8 USER’S MANUAL V1.0 ADDRESS SPACES 2-11 16-ByteContiguousworkingRegister blockRegister FileContains 328-Byte Slices0 0 0 0 0 X X

S3F84B8 USER’S MANUAL V1.0 I/O PORTS 9-1 9 I/O PORTS OVERVIEW The S3F84B8 microcontroller has three bit-programmable I/O ports, P0-P2. This give

I/O PORTS S3F84B8 USER’S MANUAL V1.0 9-2 PORT DATA REGISTERS Table 9-2 gives you an overview of the register locations of all three S3F84B8 I/O

S3F84B8 USER’S MANUAL V1.0 I/O PORTS 9-3 PORT 0 Port 0 is a 6-bit I/O Port that you can use in two ways: — General-purpose I/O — Alternative fun

I/O PORTS S3F84B8 USER’S MANUAL V1.0 9-4 Port 0 High Control Register (P0CONH)E3H, Set1, Bank0, R/W, Reset value:00HLSBMSB.7.6.5.4.3.2.1

S3F84B8 USER’S MANUAL V1.0 I/O PORTS 9-5 Port 0 Low Control Register (P0CONL)E4H, Set1, Bank0, R/W, Reset value:00HLSBMSB.7.6.5.4.3.2.1.0.5 .4 b

I/O PORTS S3F84B8 USER’S MANUAL V1.0 9-6 Port 0 External Interrupt Register (P0INT)E3H, Set1, Bank0, R/W, Reset value:00HLSBMSB.7.6.5 .4.3.2.1.0

S3F84B8 USER’S MANUAL V1.0 I/O PORTS 9-7 P0.4/INT3P0.3/INT2Port 0 Interrupt Pending Register (P0PND)E6H, Set1, Bank0, R/W, Reset value: 00H.7 .6

I/O PORTS S3F84B8 USER’S MANUAL V1.0 9-8 PORT 1 Port 1 is an3-bit I/O port that you can use in two ways: — General-purpose I/O — Alternative fun

S3F84B8 USER’S MANUAL V1.0 I/O PORTS 9-9 Port 1 Control Register (P1CON)E7H, Set1, Bank0, R/W, Reset value:00HLSBMSB.7.6.5.4.3.2.1.0.5 .4 bit/P1

I/O PORTS S3F84B8 USER’S MANUAL V1.0 9-10 Port 2 Port 2 is an 8-bit I/O port that you can use in two ways: — General-purpose I/O — Alternative f

ADDRESS SPACES S3F84B8 USER’S MANUAL V1.0 2-12 REGISTER ADDRESSING The S3C8-series register architecture provides an efficient method of working

S3F84B8 USER’S MANUAL V1.0 I/O PORTS 9-11 Port 2 Control Register, High Byte (P2CONH)E8H, Set1, Bank0, R/W, Reset value:00HLSBMSB.7.6 .5.4.3.2.1

I/O PORTS S3F84B8 USER’S MANUAL V1.0 9-12 Port 2 Control Register, Low Byte (P2CONL)E8H, Set1, Bank0, R/W, Reset value:00HLSBMSB.7.6.5.4.3.2.1.0

S3F84B8 USER’S MANUAL V1.0 I/O PORTS 9-13 NOTES

S3F84B8 USER’S MANUAL V1.0 BASIC TIMER 10-1 10 BASIC TIMER OVERVIEW Basic Timer (BT) You can use the basic timer (BT) in two different ways: —

BASIC TIMER S3F84B8 USER’S MANUAL V1.0 10-2 BASIC TIMER (BT) BASIC TIMER CONTROL REGISTER (BTCON) The basic timer control register, BTCON, is use

S3F84B8 USER’S MANUAL V1.0 BASIC TIMER 10-3 BASIC TIMER FUNCTION DESCRIPTION Watchdog Timer Function You can program the basic timer overflow sig

BASIC TIMER S3F84B8 USER’S MANUAL V1.0 10-4 Oscillation Stabilization TimeNormal Operating mode0.8 VDDtWAIT = (4096x128)/fOSCBasic timer incremen

S3F84B8 USER’S MANUAL V1.0 BASIC TIMER 10-5 NOTE: Duration of the oscillator stabilzation wait time, tWAIT, it is released by an interrupt is det

BASIC TIMER S3F84B8 USER’S MANUAL V1.0 10-6 PROGRAMMING TIP — Configuring the Basic Timer This example shows how to configure the basic timer to

S3F84B8 USER’S MANUAL V1.0 BASIC TIMER 10-7 NOTES

S3F84B8 USER’S MANUAL V1.0 ADDRESS SPACES 2-13 RP1RP0RegisterPointers00HAllAddressingModesPage 0Indirect Register,IndexedAddressingModesPage 0Re

S3F84B8 USER’S MANUAL V1.0 8-BIT TIMER A 11-1 11 8-BIT TIMER A OVERVIEW The 8-bit timer A is an 8-bit general-purpose timer/counter. Timer A h

8-BIT TIMER A S3F84B8 USER’S MANUAL V1.0 11-2 FUNCTION DESCRIPTION Timer A Interrupts The timer A module can generate two interrupts: the timer

S3F84B8 USER’S MANUAL V1.0 8-BIT TIMER A 11-3 TIMER A CONTROL REGISTER (TACON) You use the timer A control register, TACON — Select the timer

8-BIT TIMER A S3F84B8 USER’S MANUAL V1.0 11-4 Figure 11-1. Timer A Control Register (TACON) Timer A Prescaler Register (TAPS)E3H, Set1, Bank1,

S3F84B8 USER’S MANUAL V1.0 8-BIT TIMER A 11-5 Timer A Data Register (TADATA)E3H, Set1, Bank1, R/WLSBMSB.7.6.5.4.3.2.1.0Reset Value: FFh Figure 1

8-BIT TIMER A S3F84B8 USER’S MANUAL V1.0 11-6 NOTES

S3F84B8 USER’S MANUAL V1.0 TIMER 0 12-1 12 TIMER 0 ONE 16-BIT TIMER MODE (TIMER 0) The 16-bit timer 0 is used in one 16-bit timer or two 8-bit t

TIMER 0 S3F84B8 USER’S MANUAL V1.0 12-2 Timer 0 Control Register (TCCON) You can use timer 0 control register, TCCON, to — Enable the timer 0 oper

S3F84B8 USER’S MANUAL V1.0 TIMER 0 12-3 Timer C Prescaler Register (TCPS)E6H, Set1, Bank1, R/WLSBMSB.7.6.5.4.3.2.1.0Reset Value: 00hTimer C cloc

TIMER 0 S3F84B8 USER’S MANUAL V1.0 12-4 TWO 8-BIT TIMERS MODE (TIMER C and D) OVERVIEW The 8-bit Timer C and D are the 8-bit general-purpose timers

ADDRESS SPACES S3F84B8 USER’S MANUAL V1.0 2-14 COMMON WORKING REGISTER AREA (C0H–CFH) After a reset, register pointers RP0 and RP1 automatically

S3F84B8 USER’S MANUAL V1.0 TIMER 0 12-5 TCCON and TDCON are located in address E5H and E9H, Set1 Bank1, and are read/write addressable using reg

TIMER 0 S3F84B8 USER’S MANUAL V1.0 12-6 Timer C Prescaler Register (TCPS)E6H, Set1, Bank1, R/WLSBMSB.7.6.5.4.3.2.1.0Reset Value: 00hTimer C clock s

S3F84B8 USER’S MANUAL V1.0 TIMER 0 12-7 Timer B Control Register (TDCON)E9H, Set1, Bank1, Reset = 00H, R/W.7 .6 .5 .4 .3 .2 .1 .0MSB LSBTimer D

TIMER 0 S3F84B8 USER’S MANUAL V1.0 12-8 FUNCTION DESCRIPTION Interval Timer Function (Timer C and Timer D) The Timer C and D module can generate an

S3F84B8 USER’S MANUAL V1.0 TIMER 0 12-9 NOTE:When TCCON.7 is '0', two 8-bit timer C/D (Interval mode).TDPS.3-.0PrescalerTCCON.4Compara

TIMER 0 S3F84B8 USER’S MANUAL V1.0 12-10 Pulse Width Modulation Mode (Timer D) Pulse width modulation (PWM) mode lets you program the width (durati

S3F84B8 USER’S MANUAL V1.0 A/D CONVERTER 13-1 13 A/D CONVERTER OVERVIEW The 10-bit A/D converter (ADC) module uses successive approximation logic

A/D CONVERTER S3F84B8 USER’S MANUAL V1.0 13-2 USING A/D PINS FOR STANDARD DIGITAL INPUT The ADC module's input pins are alternatively used a

S3F84B8 USER’S MANUAL V1.0 A/D CONVERTER 13-3 INTERNAL REFERENCE VOLTAGE LEVELS In the ADC function block, the analog input voltage level is compa

A/D CONVERTER S3F84B8 USER’S MANUAL V1.0 13-4 50 ADC ClockADCON.0 1. . .40 ClockPreviousValueValidDataSet uptime10 clockADDATAH (8-Bit)

S3F84B8 USER’S MANUAL V1.0 ADDRESS SPACES 2-15  PROGRAMMING TIP — Addressing the Common Working Register Area As the following examples show, y

S3F84B8 USER’S MANUAL V1.0 A/D CONVERTER 13-5 INTERNAL A/D CONVERSION PROCEDURE 1. Analog input must remain between the voltage range of VSS and

A/D CONVERTER S3F84B8 USER’S MANUAL V1.0 13-6 ) PROGRAMMING TIP – Configuring A/D Converter ;-----------------<< Interrupt Vector Address

S3F84B8 USER’S MANUAL V1.0 A/D CONVERTER 13-7 ) PROGRAMMING TIP – Configuring A/D Converter (Continued) INT_ADC: LD R2, ADDATAH ; LD R3, ADDAT

A/D CONVERTER S3F84B8 USER’S MANUAL V1.0 13-8 NOTES

S3F84B8 USER’S MANUAL V1.0 COMPARATOR 14-1 14 COMPARATOR OVERVIEW This microcontroller has 4 comparators. The operation of 4 comparators is ind

COMPARATOR S3F84B8 USER’S MANUAL V1.0 14-2 CMP0 Control Register (CMP0CON)EAH, Set1, Bank0, Reset = 02H, R/W.7 .6 .5 .4 .3 .2 .1 .0MSB LSBCMP0

S3F84B8 USER’S MANUAL V1.0 COMPARATOR 14-3 BLOCK DIAGRAM Figure 14-3 Comparator 0 diagram COMPARATOR1/2/3 Comparator 1, 2 and 3 has the same s

COMPARATOR S3F84B8 USER’S MANUAL V1.0 14-4 read/write addressable (except CMP1/2/3CON.1) using Register addressing mode. To enable comparator1/2

S3F84B8 USER’S MANUAL V1.0 COMPARATOR 14-5 CMP2 Control Register (CMP2CON)ECH, Set1, Bank0, Reset = 02H, R/W.7 .6 .5 .4 .3 .2 .1 .0MSB LSBCMP2

COMPARATOR S3F84B8 USER’S MANUAL V1.0 14-6 CMP Interrupt Mode Control Register (CMPINT)EDH, Set1, Bank0, Reset = FFH, R/W.7 .6 .5 .4 .3 .2 .1 .

ADDRESS SPACES S3F84B8 USER’S MANUAL V1.0 2-16 Together they create an8-bit register addressRegister pointerprovides fivehigh-order bitsAddress

S3F84B8 USER’S MANUAL V1.0 COMPARATOR 14-7  PROGRAMMING TIP —comparator configuration • • DI LD CMPINT, #055H ; Falling edge interrupt

COMPARATOR S3F84B8 USER’S MANUAL V1.0 14-8 NOTES

S3F84B8 USER’S MANUAL V1.0 OPAMP 15-1 15 OPERATIONAL AMPLIFIER OVERVIEW This microcontroller has an Operational Amplifier. The operation of th

OPAMP S3F84B8 USER’S MANUAL V1.0 15-2 OPAMP CONTROL REGISTER (OPACON) You use OPAMP control register, OPACON — Enable OPAMP — Select operating

S3F84B8 USER’S MANUAL V1.0 OPAMP 15-3 REFERENCE CIRCUIT Figure 15-3. OPAMP Application reference circuit @ gain=10

OPAMP S3F84B8 USER’S MANUAL V1.0 15-4 NOTES

S3F84B8 USER’S MANUAL V1.0 10-BIT IH-PWM 16-1 16 10-BIT IH-PWM OVERVIEW This microcontroller has a 10-bit IH-PWM circuit that can cooperate wi

10-BIT IH-PWM S3F84B8 USER’S MANUAL V1.0 16-2 Table 16-1. PWM Control and Data Registers Register Name Mnemonic Address Location Function PWM d

S3F84B8 USER’S MANUAL V1.0 10-BIT IH-PWM 16-3 PWM CONTROL REGISTER (PWMCON) The control register for the PWM module, PWMCON, is located at regis

10-BIT IH-PWM S3F84B8 USER’S MANUAL V1.0 16-4 PWM CMP LINKAGE CONTROL REGISTER (PWMCCON) The control register for the linkage of CMP and PWM modu

S3F84B8 USER’S MANUAL V1.0 ADDRESS SPACES 2-17 8-BIT WORKING REGISTER ADDRESSING You can also use 8-bit working register addressing to access re

S3F84B8 USER’S MANUAL V1.0 10-BIT IH-PWM 16-5 LSBMSBPWM Delay trigger Registers (PWMDL) F5H, Set 1, Bank 0, Reset=00H, R/W----.3.2.1.0Delay Time

10-BIT IH-PWM S3F84B8 USER’S MANUAL V1.0 16-6 Figure 16-7. An example of the cooperation of PWM and Comparator 0_Delay Trigger Figure 16-8. A

S3F84B8 USER’S MANUAL V1.0 10-BIT IH-PWM 16-7 Figure 16-9. An example of the cooperation of PWM and Comparator 1/2/3 _ Hard Lock Figure 16-1

10-BIT IH-PWM S3F84B8 USER’S MANUAL V1.0 16-8 NOTES

S3F84B8 USER’S MANUAL V1.0 PROGRAMABLE BUZZER 17-1 17 PROGRAMABLE BUZZER OVERVIEW This microcontroller has integrated a programmable buzzer. T

PROGRAMABLE BUZZER S3F84B8 USER’S MANUAL V1.0 17-2 BUZ FREQUENCY TABLE （@4MHZ） Output frequency (KHz) Output frequency (KHz) BUZCON f/16 f/32 f

S3F84B8 USER’S MANUAL V1.0 PROGRAMABLE BUZZER 17-3 ClearMatchBUZCON.7-.6fosc/128BUZOUT(P0.3)Data Bus8MUX5-bit Up-Counter5-bit ComparatorBUZ Buf

PROGRAMABLE BUZZER S3F84B8 USER’S MANUAL V1.0 17-4 NOTES

S3F84B8 USER’S MANUAL V1.0 S3F84B8 FLASH MCU 18-1 18 S3F84B8 FLASH MCU OVERVIEW The S3F84B8 single-chip CMOS microcontroller has an on-chip Flash

S3F84B8 FLASH MCU S3F84B8 USER’S MANUAL V1.0 18-2 S3F84B820-DIP/ 20-SOP2019181716151413121112345678910VDDP2.7/ADC7/(SCL)P2.6/ADC6/(SDA)P2.5/ADC5/

ADDRESS SPACES S3F84B8 USER’S MANUAL V1.0 2-18 8-bit addressform instruction'LD R11, R2'RP00 1 1 0 0 0 0 01 1 0 0 1 0

S3F84B8 USER’S MANUAL V1.0 EMBEDDED FLASH MEMORY INTERFACE 19-1 19 EMBEDDED FLASH MEMORY INTERFACE OVERVIEW The S3F84B8 has an on-chip flash mem

EMBEDDED FLASH MEMORY INTERFACE S3F84B8 USER’S MANUAL V1.0 19-2 User Program Mode This mode supports sector erase, byte programming, byte read a

S3F84B8 USER’S MANUAL V1.0 EMBEDDED FLASH MEMORY INTERFACE 19-3 SMART OPTION Smart option is the program memory option for starting condition of

EMBEDDED FLASH MEMORY INTERFACE S3F84B8 USER’S MANUAL V1.0 19-4 FLASH MEMORY CONTROL REGISTERS (USER PROGRAM MODE) FLASH MEMORY CONTROL REGISTER

S3F84B8 USER’S MANUAL V1.0 EMBEDDED FLASH MEMORY INTERFACE 19-5 FLASH MEMORY SECTOR ADDRESS REGISTERS There are two sector address registers fo

EMBEDDED FLASH MEMORY INTERFACE S3F84B8 USER’S MANUAL V1.0 19-6 SECTOR ERASE User can erase a flash memory partially by using sector erase funct

S3F84B8 USER’S MANUAL V1.0 EMBEDDED FLASH MEMORY INTERFACE 19-7 The Sector Erase Procedure in User Program Mode 1. Set Flash Memory User Progra

EMBEDDED FLASH MEMORY INTERFACE S3F84B8 USER’S MANUAL V1.0 19-8  PROGRAMMING TIP — Sector Erase Case1. Erase one sector • • ERA

S3F84B8 USER’S MANUAL V1.0 EMBEDDED FLASH MEMORY INTERFACE 19-9 PROGRAMMING A flash memory is programmed in one-byte unit after sector erase. T

EMBEDDED FLASH MEMORY INTERFACE S3F84B8 USER’S MANUAL V1.0 19-10 SB1Start; Select Bank1; User Program Mode Enable; Set Secotr Base Address; W

S3F84B8 USER’S MANUAL V1.0 ADDRESS SPACES 2-19 SYSTEM AND USER STACK The S3C8-series microcontrollers use the system stack for data storage, sub

S3F84B8 USER’S MANUAL V1.0 EMBEDDED FLASH MEMORY INTERFACE 19-11 SB1Start; Select Bank1; User Program Mode Enable; Set Secotr Base Address; W

EMBEDDED FLASH MEMORY INTERFACE S3F84B8 USER’S MANUAL V1.0 19-12 　PROGRAMMING TIP — Programming Case1. 1-Byte Programming • • WR_BYTE:

S3F84B8 USER’S MANUAL V1.0 EMBEDDED FLASH MEMORY INTERFACE 19-13 Case3. Programming to the flash memory space located in other sectors • • WR_I

EMBEDDED FLASH MEMORY INTERFACE S3F84B8 USER’S MANUAL V1.0 19-14 READING The read operation starts by ‘LDC’ instruction. The program procedure

S3F84B8 USER’S MANUAL V1.0 EMBEDDED FLASH MEMORY INTERFACE 19-15 HARD LOCK PROTECTION User can set Hard Lock Protection by writing ‘0110B’ in FM

EMBEDDED FLASH MEMORY INTERFACE S3F84B8 USER’S MANUAL V1.0 19-16 NOTES

S3F84B8 USER’S MANUAL V1.0 LOW VOLTAGE RESET 20-1 20 LOW VOLTAGE RESET OVERVIEW By smart option (3FH.7 in ROM), user can select internal RESET

LOW VOLTAGE RESET S3F84B8 USER’S MANUAL V1.0 20-2 +-VREFBGR VDDVREFVIN VDDN.FnRESETWhen the VDD levelis lower than VLVR ComparatorNotes:BGR is B

S3F84B8 USER’S MANUAL V1.00 ELECTRICAL DATA 21-1 21 ELECTRICAL DATA OVERVIEW In this section, the following S3F84B8 electrical characteristics ar

ELECTRICAL DATA S3F84B8 USER’S MANUAL V1.00 21-2 Table 21-1. Absolute Maximum Ratings (TA = 25 °C) Parameter Symbol Conditions Rating Unit Su

S3F84B8 USER'S MANUAL V1.0 PRODUCT OVERVIEW 1-3 BLOCK DIAGRAM I/ O Port and Interrupt ControlSAM8 RC CPU8- KbyteROM272 - ByteRAMOSC/nRESET8

ADDRESS SPACES S3F84B8 USER’S MANUAL V1.0 2-20  PROGRAMMING TIP — Standard Stack Operations Using PUSH and POP The following example shows you

S3F84B8 USER’S MANUAL V1.00 ELECTRICAL DATA 21-3 Table 21-2. DC Electrical Characteristics (TA = – 40 °C to + 85 °C, VDD = 1.8 V to 5.5 V

ELECTRICAL DATA S3F84B8 USER’S MANUAL V1.00 21-4 NOTE: Supply current does not include current drawn through internal pull-up resistors or exter

S3F84B8 USER’S MANUAL V1.00 ELECTRICAL DATA 21-5 Table 21-4. Oscillator Characteristics (TA = – 40°C to + 85 °C) Oscillator Clock Circuit T

ELECTRICAL DATA S3F84B8 USER’S MANUAL V1.00 21-6 10 MHzExternal Clock Frequency8 MHz1 MHz11.84567Supply Voltage (V)2 MHz3 MHz4 MHz..5.54.52.7400K

S3F84B8 USER’S MANUAL V1.00 ELECTRICAL DATA 21-7 Table 21-6. Data Retention Supply Voltage in Stop Mode (TA = – 40 °C to + 85 °C, VDD = 1.8

ELECTRICAL DATA S3F84B8 USER’S MANUAL V1.00 21-8 Table 21-7. A/D Converter Electrical Characteristics (TA = – 40 °C to + 85 °C, VDD = 1.8 V

S3F84B8 USER’S MANUAL V1.00 ELECTRICAL DATA 21-9 Table 21-1. OPAMP electrical characteristics (TA = - 40 　C to + 85　C , VDD = 2.0 V to 5.

ELECTRICAL DATA S3F84B8 USER’S MANUAL V1.00 21-10 Table 21-1. Comparator electrical characteristics (TA = - 40 　C to + 85　C , VDD = 2.0 V

S3F84B8 USER’S MANUAL V1.00 ELECTRICAL DATA 21-11 Table 21-8. LVR Circuit Characteristics (TA = 25 °C, VDD = 1.8 V to 5.5 V) Parameter Symb

ELECTRICAL DATA S3F84B8 USER’S MANUAL V1.00 21-12 Figure 21-6. The Circuit Diagram to Improve EFT Characteristics Table 21-9 ESD Characteris

S3F84B8 USER’S MANUAL V1.0 ADDRESS SPACES 2-21 NOTES

S3F84B8 USER’S MANUAL V1.00 ELECTRICAL DATA 21-13 NOTES

S3F84B8 USER’S MANUAL V1.0 DEVELOPMENT TOOLS 22-1 22 DEVELOPMENT TOOLS OVERVIEW Samsung provide a powerful and ease-to-use development support sy

DEVELOPMENT TOOLS S3F84B8 USER’S MANUAL V1.0 22-2 [Development System Configuration] Figure 22-1. Development System Configuration

S3F84B8 USER’S MANUAL V1.0 DEVELOPMENT TOOLS 22-3 TB84B8 TARGET BOARD The TB84B8 target board is used for the S3F84B8 microcontrollers. The TB84B

DEVELOPMENT TOOLS S3F84B8 USER’S MANUAL V1.0 22-4 Table 22-1. Power Selection Settings for TB84B8 "To User_Vcc" Settings Operating Mod

S3F84B8 USER’S MANUAL V1.0 DEVELOPMENT TOOLS 22-5 Table 22-3. Using Single Header Pins to Select Clock Source and Enable/Disable PWM Target Board

DEVELOPMENT TOOLS S3F84B8 USER’S MANUAL V1.0 22-6 ONOFFLowHigh (Default)NOTE: 1. For EVA chip, smart option is determined by DIP switch not soft

S3F84B8 USER’S MANUAL V1.0 DEVELOPMENT TOOLS 22-7 (Top View)56S3C84T5S320-PIN DIP SOCKET24681013579VDDP2.7/ADC7/(SCL)P2.6/ADC6/(SDA)P2.5/ADC5/CM

DEVELOPMENT TOOLS S3F84B8 USER’S MANUAL V1.0 22-8 Third parties for Development Tools SAMSUNG provides a complete line of development tools for

S3F84B8 USER’S MANUAL V1.0 DEVELOPMENT TOOLS 22-9 OTP/MTP PROGRAMMER (WRITER) SPW-uni Single OTP/ MTP/FLASH Programmer • Download/Upload and d

S3F84B8 USER’S MANUAL V1.0 ADDRESSING MODES 3-1 3 ADDRESSING MODES OVERVIEW Instructions that are stored in program memory are fetched for execu

DEVELOPMENT TOOLS S3F84B8 USER’S MANUAL V1.0 22-10 OTP/MTP PROGRAMMER (WRITER) (Continued) AS-pro On-board programmer for Samsung Flash MCU

S3F84B8 USER’S MANUAL V1.0 DEVELOPMENT TOOLS 22-11

DEVELOPMENT TOOLS S3F84B8 USER’S MANUAL V1.0 22-12 NOTES

S3F84B8 USER’S MANUAL V1.0 MECHANICAL DATA 23-1 23 MECHANICAL DATA OVERVIEW The S3F84B8 is available in a 20-pin DIP package (Samsung: 20-DIP-300A

MECHANICAL DATA S3F84B8 USER’S MANUAL V1.0 23-2 NOTE: Dimensions are in millimeters.20-SOP-37510.30 ± 0.30#11#20#1#1013.14 MAX12.74 ± 0.20(0.66

ADDRESSING MODES S3F84B8 USER’S MANUAL V1.0 3-2 REGISTER ADDRESSING MODE (R) In Register addressing mode (R), the operand value is the content o

S3F84B8 USER’S MANUAL V1.0 ADDRESSING MODES 3-3 INDIRECT REGISTER ADDRESSING MODE (IR) In Indirect Register (IR) addressing mode, the content of

ADDRESSING MODES S3F84B8 USER’S MANUAL V1.0 3-4 INDIRECT REGISTER ADDRESSING MODE (Continued) dstOPCODEPAIRPoints toRegister PairExampleInstruct

S3F84B8 USER’S MANUAL V1.0 ADDRESSING MODES 3-5 INDIRECT REGISTER ADDRESSING MODE (Continued) dstOPCODEADDRESS4-bitWorkingRegisterAddressPoint t

ADDRESSING MODES S3F84B8 USER’S MANUAL V1.0 3-6 INDIRECT REGISTER ADDRESSING MODE (Concluded) dstOPCODE4-bit WorkingRegister AddressSample Instr

S3F84B8 USER’S MANUAL V1.0 ADDRESSING MODES 3-7 INDEXED ADDRESSING MODE (X) Indexed (X) addressing mode adds an offset value to a base address d

ADDRESSING MODES S3F84B8 USER’S MANUAL V1.0 3-8 INDEXED ADDRESSING MODE (Continued) Register FileOPERANDProgram MemoryorData MemoryPoint to Work

PRODUCT OVERVIEW S3F84B8 USER'S MANUAL V1.0 1-4 PIN ASSIGNMENTS S3F84B820-DIP/ 20-SOP2019181716151413121112345678910VDDP2.7/ADC7/(SCL)P2.

S3F84B8 USER’S MANUAL V1.0 ADDRESSING MODES 3-9 INDEXED ADDRESSING MODE (Concluded) Register FileOPERANDProgram MemoryorData MemoryPoint to Work

ADDRESSING MODES S3F84B8 USER’S MANUAL V1.0 3-10 DIRECT ADDRESS MODE (DA) In Direct Address (DA) mode, the instruction provides the operand&apos

S3F84B8 USER’S MANUAL V1.0 ADDRESSING MODES 3-11 DIRECT ADDRESS MODE (Continued) OPCODEProgram MemoryLower Address ByteMemoryAddressUsedUpper Ad

ADDRESSING MODES S3F84B8 USER’S MANUAL V1.0 3-12 INDIRECT ADDRESS MODE (IA) In Indirect Address (IA) mode, the instruction specifies an address

S3F84B8 USER’S MANUAL V1.0 ADDRESSING MODES 3-13 RELATIVE ADDRESS MODE (RA) In Relative Address (RA) mode, a twos-complement signed displacement

ADDRESSING MODES S3F84B8 USER’S MANUAL V1.0 3-14 IMMEDIATE MODE (IM) In Immediate (IM) addressing mode, the operand value used in the instructio

S3F84B8 USER’S MANUAL V1.0 ADDRESSING MODES 3-15 NOTES

S3F84B8 USER’S MANUAL V1.0 CONTROL REGISTER 4-1 4 CONTROL REGISTERS OVERVIEW In this section, detailed descriptions of the S3F84B8 control regis

CONTROL REGISTERS S3F84B8 USER’S MANUAL V1.0 4-2 Table 4-1. System and Peripheral Control Registers Set1 Bank0 Register name Mnemonic Address

S3F84B8 USER’S MANUAL V1.0 CONTROL REGISTER 4-3 Table 4-1. System and Peripheral Control Registers Set1 Bank 0(Continued) Register Name Mnemoni

S3F84B8 USER'S MANUAL V1.0 PRODUCT OVERVIEW 1-5 PIN DESCRIPTIONS Table 1-1. Pin Descriptions of 20-DIP (20-SOP) Pin Names Pin Type Pin Desc

CONTROL REGISTERS S3F84B8 USER’S MANUAL V1.0 4-4 Table 4-1. System and Peripheral Control Registers Set1 Bank1 Register name Mnemonic Address

S3F84B8 USER’S MANUAL V1.0 CONTROL REGISTER 4-5 FLAGS - System Flags Register.7.6.5Bit IdentifierRESET ValueRead/WriteR = Read-onlyW = Write-onl

CONTROL REGISTERS S3F84B8 USER’S MANUAL V1.0 4-6 ADCON — A/D Converter Control Register FAH, BANK0 Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 RE

S3F84B8 USER’S MANUAL V1.0 CONTROL REGISTER 4-7 AMTDATA —Anti-mis-trigger Data Register F6H, BANK0

CONTROL REGISTERS S3F84B8 USER’S MANUAL V1.0 4-8 BTCON — Basic Timer Control Register D3H, BANK0 Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 RE

S3F84B8 USER’S MANUAL V1.0 CONTROL REGISTER 4-9 BUZCON — BUZ control Register F7H

CONTROL REGISTERS S3F84B8 USER’S MANUAL V1.0 4-10 CLKCON — Clock Control Register D4H, BANK0 Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 RESET Va

S3F84B8 USER’S MANUAL V1.0 CONTROL REGISTER 4-11 CMP0CON — Comparator0 Control Register EAH, BANK0 Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0

CONTROL REGISTERS S3F84B8 USER’S MANUAL V1.0 4-12 CMP1CON — Comparator1 Control Register EBH, BANK0 Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0

S3F84B8 USER’S MANUAL V1.0 CONTROL REGISTER 4-13 CMP2CON — Comparator1 Control Register ECH, BANK0 Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 R

PRODUCT OVERVIEW S3F84B8 USER'S MANUAL V1.0 1-6 PIN CIRCUITS P-ChannelN-ChannelVDDOutOutput DisableData Figure 1-3. Pin Circuit Type 1 P-Ch

CONTROL REGISTERS S3F84B8 USER’S MANUAL V1.0 4-14 CMP3CON — Comparator1 Control Register EDH, BANK0 Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0

S3F84B8 USER’S MANUAL V1.0 CONTROL REGISTER 4-15 CMPINT— Comparator Interrupt Mode Control Register EEH, BANK0 Bit Identifier .7 .6 .5 .4

CONTROL REGISTERS S3F84B8 USER’S MANUAL V1.0 4-16 FLAGS — System Flags Register

S3F84B8 USER’S MANUAL V1.0 CONTROL REGISTER 4-17 FMCON — Flash Memory Control Register F5H, BANK1 Bit Identifier .7 .6 .5 .4 .3 .2

CONTROL REGISTERS S3F84B8 USER’S MANUAL V1.0 4-18 FMSECH — Flash Memory Sector Address Register (High Byte) F7H, BANK1 Bit Identifier .7 .6

S3F84B8 USER’S MANUAL V1.0 CONTROL REGISTER 4-19 FMUSR — Flash Memory User Programming Enable Register F6H, BANK1 Bit Identifier .7 .6 .5 .4 .3

CONTROL REGISTERS S3F84B8 USER’S MANUAL V1.0 4-20 IMR — Interrupt Mask Register DDH, BANK0 Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 Reset Valu

S3F84B8 USER’S MANUAL V1.0 CONTROL REGISTER 4-21 IPH — Instruction Pointer (High Byte) DAH, BANK0 Bit Identifier .

CONTROL REGISTERS S3F84B8 USER’S MANUAL V1.0 4-22 IPR — Interrupt Priority Register FFH, BANK0 Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 Reset

S3F84B8 USER’S MANUAL V1.0 CONTROL REGISTER 4-23 IRQ — Interrupt Request Register DCH, BANK0 Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 Reset Va

S3F84B8 USER'S MANUAL V1.0 PRODUCT OVERVIEW 1-9 VDDI/ODigital InputPull-upenableOutput Disable(Input Mode)DataAnalog InputEnableAnalog Inpu

CONTROL REGISTERS S3F84B8 USER’S MANUAL V1.0 4-24 OPACON — OP AMP Control Register E0H, BANK1 Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 RESET V

S3F84B8 USER’S MANUAL V1.0 CONTROL REGISTER 4-25 P0CONH — Port 0 Control Register (High Byte) E4H, Bank0 Bit Identifier .7 .6 .5 .4 .3 .2 .1

CONTROL REGISTERS S3F84B8 USER’S MANUAL V1.0 4-26 P0CONL — Port 0 Control Register (Low Byte) E5H, BANK0 Bit Identifier .7 .6 .5 .4 .3 .2 .1

S3F84B8 USER’S MANUAL V1.0 CONTROL REGISTER 4-27 P0INT — Port 0 Interrupt Control Register E3H, BANK0 Bit Ide

CONTROL REGISTERS S3F84B8 USER’S MANUAL V1.0 4-28 P0PND — Port 0 Interrupt Pending Register E6H, BANK0 Bit Identifier .7 .6 .5 .4 .3 .2 .1

S3F84B8 USER’S MANUAL V1.0 CONTROL REGISTER 4-29 P1CON — Port 1 Control Register E7H, BANK0 Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 RESET

CONTROL REGISTERS S3F84B8 USER’S MANUAL V1.0 4-30 P2CONH — Port 2 Control Register (High Byte) E8H, BANK0 Bit Identifier .7 .6 .5

S3F84B8 USER’S MANUAL V1.0 CONTROL REGISTER 4-31 P2CONL — Port 2 Control Register (Low Byte) E9H, BANK0 Bit Identifier .7 .6 .5 .4 .3 .2 .1

CONTROL REGISTERS S3F84B8 USER’S MANUAL V1.0 4-32 PWMCON — PWM Control Register EFH, BANK0 Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 RESET Val

S3F84B8 USER’S MANUAL V1.0 CONTROL REGISTER 4-33 PWMCCON — PWM CMP Control Register

PRODUCT OVERVIEW S3F84B8 USER'S MANUAL V1.0 1-10 VDDI/ODigital InputPull-upenableOutput Disable(Input Mode)DataAnalog InputEnableAnalog Inp

CONTROL REGISTERS S3F84B8 USER’S MANUAL V1.0 4-34 PWMDL — Comparator0 Output Delay Register F5H, Bank0

S3F84B8 USER’S MANUAL V1.0 CONTROL REGISTER 4-35 RESETID — Reset Source Indicating Register F2H, BANK1

CONTROL REGISTERS S3F84B8 USER’S MANUAL V1.0 4-36 RP0 — Register Pointer 0 D6H, BANK0 Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 Reset Value 1 1

S3F84B8 USER’S MANUAL V1.0 CONTROL REGISTER 4-37 SPL — Stack Pointer D9H, BANK0 Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 Reset Value x x x

CONTROL REGISTERS S3F84B8 USER’S MANUAL V1.0 4-38 SYM — System Mode Register DEH, BANK0 Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 Reset Value 0

S3F84B8 USER’S MANUAL V1.0 CONTROL REGISTER 4-39 TACON — Timer A Control Register E

CONTROL REGISTERS S3F84B8 USER’S MANUAL V1.0 4-40 TAPS —TA Pre-scalar Register

S3F84B8 USER’S MANUAL V1.0 CONTROL REGISTER 4-41 TCCON — Timer C Control Register E5

CONTROL REGISTERS S3F84B8 USER’S MANUAL V1.0 4-42 TCPS —TC Pre-scalar Register

S3F84B8 USER’S MANUAL V1.0 CONTROL REGISTER 4-43 TDCON — Timer D Control Register E9

S3F84B8 USER'S MANUAL V1.0 PRODUCT OVERVIEW 1-9 I/OOutput DisableData Pin CircuitType 1Pull-upEnableVDDPull-up register(50 kohm typical)No

CONTROL REGISTERS S3F84B8 USER’S MANUAL V1.0 4-44 TDPS —TD Pre-scalar Register

S3F84B8 USER’S MANUAL V1.0 INTERRUPT STRUCTURE 5-1 5 INTERRUPT STRUCTURE OVERVIEW The S3C8/S3F8-series interrupt structure has three basic compo

INTERRUPT STRUCTURE S3F84B8 USER’S MANUAL V1.0 5-2 INTERRUPT TYPES The three components of the S3C8/S3F8 interrupt structure described before —

S3F84B8 USER’S MANUAL V1.0 INTERRUPT STRUCTURE 5-3 S3F84B8 INTERRUPT STRUCTURE The S3F84B8 microcontroller supports 17 interrupt sources. Every

INTERRUPT STRUCTURE S3F84B8 USER’S MANUAL V1.0 5-4 Interrupt Vector Addresses All interrupt vector addresses for the S3F84B8 interrupt structure

S3F84B8 USER’S MANUAL V1.0 INTERRUPT STRUCTURE 5-5 Enable/Disable Interrupt Instructions (EI, DI) Executing the Enable Interrupts (EI) instructi

INTERRUPT STRUCTURE S3F84B8 USER’S MANUAL V1.0 5-6 INTERRUPT PROCESSING CONTROL POINTS Interrupt processing can therefore be controlled in two w

S3F84B8 USER’S MANUAL V1.0 INTERRUPT STRUCTURE 5-7 PERIPHERAL INTERRUPT CONTROL REGISTERS For each interrupt source there is one or more corresp

INTERRUPT STRUCTURE S3F84B8 USER’S MANUAL V1.0 5-8 SYSTEM MODE REGISTER (SYM) The system mode register, SYM (DEH, Set1), is used to globally ena

S3F84B8 USER’S MANUAL V1.0 INTERRUPT STRUCTURE 5-9 INTERRUPT MASK REGISTER (IMR) The interrupt mask register, IMR (DDH, Set1) is used to enable