Samsung YP-P10 User Manual

S3C2440A32-BIT CMOSMICROCONTROLLERUSER'S MANUALRevision 1

x S3C2440A MICROCONTROLLERTable of Contents (Continued)Chapter 7 Clock & Power ManagementOverview...

ARM INSTRUCTION SET S3C2440A RISC MICROPROCESSOR3-16IMMEDIATE OPERAND ROTATESThe immediate operand rotate field is a 4 bit unsigned integer which spe

S3C2440A RISC MICROPROCESSOR ARM INSTRUCTION SET3-17ASSEMBLER SYNTAX• MOV,MVN (single operand instructions).<opcode>{cond}{S} Rd,<Op2>• CM

ARM INSTRUCTION SET S3C2440A RISC MICROPROCESSOR3-18PSR TRANSFER (MRS, MSR)The instruction is only executed if the condition is true. The various con

S3C2440A RISC MICROPROCESSOR ARM INSTRUCTION SET3-19MSR (transfer register contents or immediate value to PSR flag bits only)Cond Source operandPd1010

ARM INSTRUCTION SET S3C2440A RISC MICROPROCESSOR3-20RESERVED BITSOnly twelve bits of the PSR are defined in ARM920T (N,Z,C,V,I,F, T & M[4:0]); th

S3C2440A RISC MICROPROCESSOR ARM INSTRUCTION SET3-21ASSEMBLY SYNTAX• MRS - transfer PSR contents to a registerMRS{cond} Rd,<psr>• MSR - transfer

ARM INSTRUCTION SET S3C2440A RISC MICROPROCESSOR3-22MULTIPLY AND MULTIPLY-ACCUMULATE (MUL, MLA)The instruction is only executed if the condition is t

S3C2440A RISC MICROPROCESSOR ARM INSTRUCTION SET3-23If the Operands Are Interpreted as SignedOperand A has the value -10, operand B has the value 20,

ARM INSTRUCTION SET S3C2440A RISC MICROPROCESSOR3-24CPSR FLAGSSetting the CPSR flags is optional, and is controlled by the S bit in the instruction.

S3C2440A RISC MICROPROCESSOR ARM INSTRUCTION SET3-25MULTIPLY LONG AND MULTIPLY-ACCUMULATE LONG (MULL, MLAL)The instruction is only executed if the con

S3C2440A MICROCONTROLLER xiTable of Contents (Continued)Chapter 9 I/O PORTSOverview...

ARM INSTRUCTION SET S3C2440A RISC MICROPROCESSOR3-26OPERAND RESTRICTIONS• R15 must not be used as an operand or as a destination register.• RdHi, R

S3C2440A RISC MICROPROCESSOR ARM INSTRUCTION SET3-27ASSEMBLER SYNTAXTable 3-5. Assembler Syntax DescriptionsMnemonic Description PurposeUMULL{cond}{S}

ARM INSTRUCTION SET S3C2440A RISC MICROPROCESSOR3-28SINGLE DATA TRANSFER (LDR, STR)The instruction is only executed if the condition is true. The var

S3C2440A RISC MICROPROCESSOR ARM INSTRUCTION SET3-29OFFSETS AND AUTO-INDEXINGThe offset from the base may be either a 12 bit unsigned binary immediate

ARM INSTRUCTION SET S3C2440A RISC MICROPROCESSOR3-30LDR from word aligned addressA+3AA+2A+1memory241680ABCDregister241680ABCDLDR from address offset

S3C2440A RISC MICROPROCESSOR ARM INSTRUCTION SET3-31USE OF R15Write-back must not be specified if R15 is specified as the base register (Rn). While us

ARM INSTRUCTION SET S3C2440A RISC MICROPROCESSOR3-32ASSEMBLER SYNTAX<LDR|STR>{cond}{B}{T} Rd,<Address>where:LDR Load from memory into a r

S3C2440A RISC MICROPROCESSOR ARM INSTRUCTION SET3-33EXAMPLESSTR R1,[R2,R4]! ; Store R1 at R2+R4 (both of which are registers); and write back address

ARM INSTRUCTION SET S3C2440A RISC MICROPROCESSOR3-34HALFWORD AND SIGNED DATA TRANSFER (LDRH/STRH/LDRSB/LDRSH)The instruction is only executed if the

S3C2440A RISC MICROPROCESSOR ARM INSTRUCTION SET3-3531 27 19 15Cond28 16 11122123120L Rn Rd[3:0] Immediate Offset (Low Nibble)[6][5] S H 0 0 = SWP in

xii S3C2440A MICROCONTROLLERTable of Contents (Continued)Chapter 10 Basic TimerOverview...

ARM INSTRUCTION SET S3C2440A RISC MICROPROCESSOR3-36HALFWORD LOAD AND STORESSetting S=0 and H=1 may be used to transfer unsigned Half-words between a

S3C2440A RISC MICROPROCESSOR ARM INSTRUCTION SET3-37Big-Endian ConfigurationA signed byte load (LDRSB) expects data on data bus inputs 31 through to 2

ARM INSTRUCTION SET S3C2440A RISC MICROPROCESSOR3-38ASSEMBLER SYNTAX<LDR|STR>{cond}<H|SH|SB> Rd,<address>LDR Load from memory into

S3C2440A RISC MICROPROCESSOR ARM INSTRUCTION SET3-39EXAMPLESLDRH R1,[R2,-R3]! ; Load R1 from the contents of the halfword address; contained in R2-R3

ARM INSTRUCTION SET S3C2440A RISC MICROPROCESSOR3-40BLOCK DATA TRANSFER (LDM, STM)The instruction is only executed if the condition is true. The vari

S3C2440A RISC MICROPROCESSOR ARM INSTRUCTION SET3-41ADDRESSING MODESThe transfer addresses are determined by the contents of the base register (Rn), t

ARM INSTRUCTION SET S3C2440A RISC MICROPROCESSOR3-42Rn1R1R12R53R1R54R7Rn0x100C0x10000x0FF40x100C0x10000x0FF40x100C0x10000x0FF40x100C0x10000x0FF4Figur

S3C2440A RISC MICROPROCESSOR ARM INSTRUCTION SET3-43Rn1R1R12R53R1R54R7Rn0x100C0x10000x0FF40x100C0x10000x0FF40x100C0x10000x0FF40x100C0x10000x0FF4Figure

ARM INSTRUCTION SET S3C2440A RISC MICROPROCESSOR3-44INCLUSION OF THE BASE IN THE REGISTER LISTWhen write-back is specified, the base is written back

S3C2440A RISC MICROPROCESSOR ARM INSTRUCTION SET3-45ASSEMBLER SYNTAX<LDM|STM>{cond}<FD|ED|FA|EA|IA|IB|DA|DB> Rn{!},<Rlist>{^}where:{

S3C2440A MICROCONTROLLER xiiiTable of Contents (Continued)Chapter 11 UARTOverview...

ARM INSTRUCTION SET S3C2440A RISC MICROPROCESSOR3-46EXAMPLESLDMFD SP!,{R0,R1,R2} ; Unstack 3 registers.STMIA R0,{R0-R15} ; Save all registers.LDMFD S

S3C2440A RISC MICROPROCESSOR ARM INSTRUCTION SET3-47SINGLE DATA SWAP (SWP)31 19 15Cond28 16 11122123B2000 Rn Rd[3:0] Source Register[15:12] Destinatio

ARM INSTRUCTION SET S3C2440A RISC MICROPROCESSOR3-48USE OF R15Do not use R15 as an operand (Rd, Rn or Rs) in a SWP instruction.DATA ABORTSIf the addr

S3C2440A RISC MICROPROCESSOR ARM INSTRUCTION SET3-49SOFTWARE INTERRUPT (SWI)The instruction is only executed if the condition is true. The various con

ARM INSTRUCTION SET S3C2440A RISC MICROPROCESSOR3-50ASSEMBLER SYNTAXSWI{cond} <expression>{cond} Two character condition mnemonic, Table 3-2.&l

S3C2440A RISC MICROPROCESSOR ARM INSTRUCTION SET3-51COPROCESSOR DATA OPERATIONS (CDP)The instruction is only executed if the condition is true. The va

ARM INSTRUCTION SET S3C2440A RISC MICROPROCESSOR3-52INSTRUCTION CYCLE TIMESCoprocessor data operations take 1S + bI incremental cycles to execute, wh

S3C2440A RISC MICROPROCESSOR ARM INSTRUCTION SET3-53COPROCESSOR DATA TRANSFERS (LDC, STC)The instruction is only executed if the condition is true. Th

ARM INSTRUCTION SET S3C2440A RISC MICROPROCESSOR3-54THE COPROCESSOR FIELDSThe CP# field is used to identify the coprocessor which is required to supp

S3C2440A RISC MICROPROCESSOR ARM INSTRUCTION SET3-55ASSEMBLER SYNTAX<LDC|STC>{cond}{L} p#,cd,<Address>LDC Load from memory to coprocessorS

xiv S3C2440A MICROCONTROLLERTable of Contents (Continued)Chapter 13 USB Device ControllerOverview...

ARM INSTRUCTION SET S3C2440A RISC MICROPROCESSOR3-56COPROCESSOR REGISTER TRANSFERS (MRC, MCR)The instruction is only executed if the condition is tru

S3C2440A RISC MICROPROCESSOR ARM INSTRUCTION SET3-57TRANSFERS TO R15When a coprocessor register transfer to ARM920T has R15 as the destination, bits 3

ARM INSTRUCTION SET S3C2440A RISC MICROPROCESSOR3-58UNDEFINED INSTRUCTIONThe instruction is only executed if the condition is true. The various condi

S3C2440A RISC MICROPROCESSOR ARM INSTRUCTION SET3-59INSTRUCTION SET EXAMPLESThe following examples show ways in which the basic ARM920T instructions c

ARM INSTRUCTION SET S3C2440A RISC MICROPROCESSOR3-60Division and RemainderA number of divide routines for specific applications are provided in sourc

S3C2440A RISC MICROPROCESSOR ARM INSTRUCTION SET3-615. Overflow in unsigned multiply accumulate with a 64 bit resultUMULL Rl,Rh,Rm,Rn ; 3 to 6 cycles

ARM INSTRUCTION SET S3C2440A RISC MICROPROCESSOR3-62Multiplication by 6ADD Ra,Ra,Ra,LSL #1 ; Multiply by 3MOV Ra,Ra,LSL#1 ; and then by 2Multiply by

S3C2440A RISC MICROPROCESSOR ARM INSTRUCTION SET3-63LOADING A WORD FROM AN UNKNOWN ALIGNMENT; Enter with address in Ra (32 bits) uses; Rb, Rc result i

ARM INSTRUCTION SET S3C2440A RISC MICROPROCESSOR3-64NOTES

S3C2440A RISC MICROPROCESSOR THUMB INSTRUCTION SET4-14 THUMB INSTRUCTION SETTHUMB INSTRUCTION SET FORMATThe thumb instruction sets are 16-bit versions

S3C2440A MICROCONTROLLER xvTable of Contents (Continued)Chapter 15 LCD ControllerOverview...

THUMB INSTRUCTION SET S3C2440A RISC MICROPROCESSOR4-2FORMAT SUMMARYThe THUMB instruction set formats are shown in the following figure.Move Shifted r

S3C2440A RISC MICROPROCESSOR THUMB INSTRUCTION SET4-3OPCODE SUMMARYThe following table summarizes the THUMB instruction set. For further information a

THUMB INSTRUCTION SET S3C2440A RISC MICROPROCESSOR4-4Table 4-1. THUMB Instruction Set Opcodes (Continued)Mnemonic Instruction Lo-RegisterOperandHi-Re

S3C2440A RISC MICROPROCESSOR THUMB INSTRUCTION SET4-5FORMAT 1: MOVE SHIFTED REGISTER15 001410[2:0] Destination Register[5:3] Source Register [10:6]

THUMB INSTRUCTION SET S3C2440A RISC MICROPROCESSOR4-6INSTRUCTION CYCLE TIMESAll instructions in this format have an equivalent ARM instruction as sho

S3C2440A RISC MICROPROCESSOR THUMB INSTRUCTION SET4-7FORMAT 2: ADD/SUBTRACT15014 10[2:0] Destination Register[5:3] Source Register [8:6] Register/Im

THUMB INSTRUCTION SET S3C2440A RISC MICROPROCESSOR4-8INSTRUCTION CYCLE TIMESAll instructions in this format have an equivalent ARM instruction as sho

S3C2440A RISC MICROPROCESSOR THUMB INSTRUCTION SET4-9FORMAT 3: MOVE/COMPARE/ADD/SUBTRACT IMMEDIATE15 0014 10[7:0] Immediate Vale[10:8] Source/Destinat

THUMB INSTRUCTION SET S3C2440A RISC MICROPROCESSOR4-10INSTRUCTION CYCLE TIMESAll instructions in this format have an equivalent ARM instruction as sh

S3C2440A RISC MICROPROCESSOR THUMB INSTRUCTION SET4-11FORMAT 4: ALU OPERATIONS15 001410[2:0] Source/Destination Register[5:3] Source Register 2 [9:6

xvi S3C2440A MICROCONTROLLERTable of Contents (Continued)Chapter 17 Real Time ClockOverview...

THUMB INSTRUCTION SET S3C2440A RISC MICROPROCESSOR4-12INSTRUCTION CYCLE TIMESAll instructions in this format have an equivalent ARM instruction as sh

S3C2440A RISC MICROPROCESSOR THUMB INSTRUCTION SET4-13FORMAT 5: HI-REGISTER OPERATIONS/BRANCH EXCHANGE15 001410[2:0] Destination Register[5:3] Source

THUMB INSTRUCTION SET S3C2440A RISC MICROPROCESSOR4-14Table 4-6. Summary of Format 5 Instructions (Continued)Op H1 H2 THUMB assembler ARM equivalent

S3C2440A RISC MICROPROCESSOR THUMB INSTRUCTION SET4-15EXAMPLESHi-Register OperationsADD PC, R5 ; PC := PC + R5 but don't set the condition codes.

THUMB INSTRUCTION SET S3C2440A RISC MICROPROCESSOR4-16FORMAT 6: PC-RELATIVE LOAD15 001410[7:0] Immediate Value[10:8] Destination RegisterWord 80 013

S3C2440A RISC MICROPROCESSOR THUMB INSTRUCTION SET4-17INSTRUCTION CYCLE TIMESAll instructions in this format have an equivalent ARM instruction. The i

THUMB INSTRUCTION SET S3C2440A RISC MICROPROCESSOR4-18FORMAT 7: LOAD/STORE WITH REGISTER OFFSET[2:0] Source/Destination Register[5:3] Base Register

S3C2440A RISC MICROPROCESSOR THUMB INSTRUCTION SET4-19OPERATIONThese instructions transfer byte or word values between registers and memory. Memory ad

THUMB INSTRUCTION SET S3C2440A RISC MICROPROCESSOR4-20FORMAT 8: LOAD/STORE SIGN-EXTENDED BYTE/HALFWORD[2:0] Destination Register[5:3] Base Register

S3C2440A RISC MICROPROCESSOR THUMB INSTRUCTION SET4-21INSTRUCTION CYCLE TIMESAll instructions in this format have an equivalent ARM instruction as sho

S3C2440A MICROCONTROLLER xviiTable of Contents (Continued)Chapter 19 MMC/SD/SDIO ControllerFeatures...

THUMB INSTRUCTION SET S3C2440A RISC MICROPROCESSOR4-22FORMAT 9: LOAD/STORE WITH IMMEDIATE OFFSET[2:0] Source/Destination Register[5:3] Base Register

S3C2440A RISC MICROPROCESSOR THUMB INSTRUCTION SET4-23OPERATIONThese instructions transfer byte or word values between registers and memory using an i

THUMB INSTRUCTION SET S3C2440A RISC MICROPROCESSOR4-24FORMAT 10: LOAD/STORE HALFWORD[2:0] Source/Destination Register[5:3] Base Register [10:6] Imm

S3C2440A RISC MICROPROCESSOR THUMB INSTRUCTION SET4-25INSTRUCTION CYCLE TIMESAll instructions in this format have an equivalent ARM instruction as sho

THUMB INSTRUCTION SET S3C2440A RISC MICROPROCESSOR4-26FORMAT 11: SP-RELATIVE LOAD/STORE[7:0] Immediate Value[10:8] Destination Register [11] Load/S

S3C2440A RISC MICROPROCESSOR THUMB INSTRUCTION SET4-27INSTRUCTION CYCLE TIMESAll instructions in this format have an equivalent ARM instruction as sho

THUMB INSTRUCTION SET S3C2440A RISC MICROPROCESSOR4-28FORMAT 12: LOAD ADDRESS[7:0] 8-bit Unsigned Constant[10:8] Destination Register [11] Source0

S3C2440A RISC MICROPROCESSOR THUMB INSTRUCTION SET4-29INSTRUCTION CYCLE TIMESAll instructions in this format have an equivalent ARM instruction as sho

THUMB INSTRUCTION SET S3C2440A RISC MICROPROCESSOR4-30FORMAT 13: ADD OFFSET TO STACK POINTER[6:0] 7-bit Immediate Value[7] Sign Flag0 = Offset is pos

S3C2440A RISC MICROPROCESSOR THUMB INSTRUCTION SET4-31FORMAT 14: PUSH/POP REGISTERS[7:0] Register List[8] PC/LR Bit0 = Do not store LR/Load PC1 = Stor

xviii S3C2440A MICROCONTROLLERTable of Contents (Continued)Chapter 21 IIS-Bus InterfaceOverview...

THUMB INSTRUCTION SET S3C2440A RISC MICROPROCESSOR4-32INSTRUCTION CYCLE TIMESAll instructions in this format have an equivalent ARM instruction as sh

S3C2440A RISC MICROPROCESSOR THUMB INSTRUCTION SET4-33FORMAT 15: MULTIPLE LOAD/STORE[7:0] Register List[10:8] Base Register[11] Load/Store Bit0 = Stor

THUMB INSTRUCTION SET S3C2440A RISC MICROPROCESSOR4-34FORMAT 16: CONDITIONAL BRANCH[7:0] 8-bit Signed Immediate[11:8] Condition15 01141 013 1211SOffs

S3C2440A RISC MICROPROCESSOR THUMB INSTRUCTION SET4-35Table 4-17. The Conditional Branch Instructions (Continued)L THUMB assembler ARM equivalent Desc

THUMB INSTRUCTION SET S3C2440A RISC MICROPROCESSOR4-36FORMAT 17: SOFTWARE INTERRUPT[7:0] Comment Field15 01141 013 1211Value 817810 91 1 1 1Figure 4-

S3C2440A RISC MICROPROCESSOR THUMB INSTRUCTION SET4-37FORMAT 18: UNCONDITIONAL BRANCH[10:0] Immediate Value15 01141 113 1211Offset110100Figure 4-19. F

THUMB INSTRUCTION SET S3C2440A RISC MICROPROCESSOR4-38FORMAT 19: LONG BRANCH WITH LINK[10:0] Long Branch and Link Offset High/Low[11] Low/High Offset

S3C2440A RISC MICROPROCESSOR THUMB INSTRUCTION SET4-39INSTRUCTION CYCLE TIMESThis instruction format does not have an equivalent ARM instruction.Table

THUMB INSTRUCTION SET S3C2440A RISC MICROPROCESSOR4-40INSTRUCTION SET EXAMPLESThe following examples show ways in which the THUMB instructions may be

S3C2440A RISC MICROPROCESSOR THUMB INSTRUCTION SET4-41GENERAL PURPOSE SIGNED DIVIDEThis example shows a general purpose signed divide and remainder ro

S3C2440A MICROCONTROLLER xixTable of Contents (Continued)Chapter 23 Camera InterfaceOverview...

THUMB INSTRUCTION SET S3C2440A RISC MICROPROCESSOR4-42Now fix up the signs of the quotient (R0) and remainder (R1)POP {R2, R3} ; Get dividend/divisor

S3C2440A RISC MICROPROCESSOR THUMB INSTRUCTION SET4-43DIVISION BY A CONSTANTDivision by a constant can often be performed by a short fixed sequence of

THUMB INSTRUCTION SET S3C2440A RISC MICROPROCESSOR4-44NOTES

S3C2440A RISC MICROPROCESSOR MEMORY CONTROLLER5-15 MEMORY CONTROLLEROVERVIEWThe S3C2440A memory controller

MEMORY CONTROLLER S3C2440A RISC MICROPROCESSOR5-20x0000_00000x0800_00000x1000_00000x1800_00000x2000_00000x2800_00000x3000_00000x3800_00000x4000_0000SR

S3C2440A RISC MICROPROCESSOR MEMORY CONTROLLER5-3Table 5-1. Bank 6/7 AddressesAddress 2MB 4MB 8MB 16MB 32M

MEMORY CONTROLLER S3C2440A RISC MICROPROCESSOR5-4FUNCTION DESCRIPTIONBANK0 BUS WIDTHThe data bus of BANK0 (nGCS0) should be configured with a width as

S3C2440A RISC MICROPROCESSOR MEMORY CONTROLLER5-5SDRAM BANK ADDRESS PIN CONNECTION EXAMPLETable 5-2. SDRAM

MEMORY CONTROLLER S3C2440A RISC MICROPROCESSOR5-6nWAIT PIN OPERATIONIf the WAIT bit(WSn bit in BWSCON) corresponding to each memory bank is enabled, t

S3C2440A RISC MICROPROCESSOR MEMORY CONTROLLER5-7nXBREQ/nXBACK Pin OperationIf nXBREQ is asserted, the S3C

Important NoticeThe information in this publication has been carefullychecked and is believed to be entirely accurate at thetime of publication. Samsu

xx S3C2440A MICROCONTROLLERTable of Contents (Continued)Chapter 23 Camera Interface (Continued)Preview Pre-Scaler Control Register 1...

MEMORY CONTROLLER S3C2440A RISC MICROPROCESSOR5-8ROM Memory Interface ExamplesA0A1A2A3A4A5A6A7A8A9A10A11A12A13A14A15D0D1D2D3D4D5D6D7nWEnOEnGCSnA0A1A2A

S3C2440A RISC MICROPROCESSOR MEMORY CONTROLLER5-9A2A3A4A5A6A7A8A9A10A11A12A13A14A15A16A17A0A1A2A3A4A5A6A7A

MEMORY CONTROLLER S3C2440A RISC MICROPROCESSOR5-10SRAM Memory Interface ExamplesA1A2A3A4A5A6A7A8A9A10A11A12A13A14A15A16D0D1D2D3D4D5D6D7D8D9D10D11D12D1

S3C2440A RISC MICROPROCESSOR MEMORY CONTROLLER5-11SDRAM Memory Interface ExamplesA1A2A3A4A5A6A7A8A9A10A11A

MEMORY CONTROLLER S3C2440A RISC MICROPROCESSOR5-12PROGRAMMABLE ACCESS CYCLETcohTcosTacsHCLKA[24:0]nGCSnOEnWEnWBED[31:0](R)D[31:0] (W)Tacc TacpTcahTacs

S3C2440A RISC MICROPROCESSOR MEMORY CONTROLLER5-13 MCLKSCKEnSCSnSCASADDRA10/APRAnSRASBADATA (CL2)DATA (CL

MEMORY CONTROLLER S3C2440A RISC MICROPROCESSOR5-14BUS WIDTH & WAIT CONTROL REGISTER (BWSCON)Register Address R/W Description Reset ValueBWSCON 0x4

S3C2440A RISC MICROPROCESSOR MEMORY CONTROLLER5-15BUS WIDTH & WAIT CONTROL REGISTER (BWSCON) (Continue

MEMORY CONTROLLER S3C2440A RISC MICROPROCESSOR5-16BANK CONTROL REGISTER (BANKCONN: NGCS0-NGCS5)Register Address R/W Description Reset ValueBANKCON0 0x

S3C2440A RISC MICROPROCESSOR MEMORY CONTROLLER5-17BANK CONTROL REGISTER (BANKCONn: nGCS6-nGCS7)Register Ad

S3C2440A MICROCONTROLLER xxiTable of Contents (Continued)Chapter 25 Bus PrioritiesOverview...

MEMORY CONTROLLER S3C2440A RISC MICROPROCESSOR5-18REFRESH CONTROL REGISTERRegister Address R/W Description Reset ValueREFRESH 0x48000024 R/W SDRAM re

S3C2440A RISC MICROPROCESSOR MEMORY CONTROLLER5-19BANKSIZE REGISTERRegister Address R/W Description Reset

MEMORY CONTROLLER S3C2440A RISC MICROPROCESSOR5-20SDRAM MODE REGISTER SET REGISTER (MRSR)Register Address R/W Description Reset ValueMRSRB6 0x4800002C

S3C2440A RISC MICROPROCESSOR NAND FLASH CONTROLLER6-16 NAND FL

NAND FLASH CONTROLLER S3C2440A RISC MICROPROCESSOR6-2BLOCK DIAGRAMSFRECCGen.Stepping Stone(4KB SRAM)Stepping Stone ControllerSYSTEMBUSNAND FLASHInterf

S3C2440A RISC MICROPROCESSOR NAND FLASH CONTROLLER6-3PIN CONFI

NAND FLASH CONTROLLER S3C2440A RISC MICROPROCESSOR6-4NAND FLASH MEMORY TIMINGHCLKCLE / ALEnWETACLS TWRPH0 TWRPH1DATA COMMAND / ADDRESSFigure 6-3. CLE

S3C2440A RISC MICROPROCESSOR NAND FLASH CONTROLLER6-5SOFTWARE

NAND FLASH CONTROLLER S3C2440A RISC MICROPROCESSOR6-6Data Register Configuration1. 16-bit NAND Flash Memory InterfaceA. Word AccessRegister Endian Bit

S3C2440A RISC MICROPROCESSOR NAND FLASH CONTROLLER6-7ECC (ERRO

S3C2440A MICROCONTROLLER xxiiiList of FiguresFigure Title PageNumber Number1-1 S3C2440A Block Diagram...

NAND FLASH CONTROLLER S3C2440A RISC MICROPROCESSOR6-8ECC MODULE FEATURESECC generation is controlled by the ECC Lock (MainECCLock, SpareECCLock) bit o

S3C2440A RISC MICROPROCESSOR NAND FLASH CONTROLLER6-9NAND FLAS

NAND FLASH CONTROLLER S3C2440A RISC MICROPROCESSOR6-10NAND FLASH MEMORY CONFIGURATIONI/O7I/O6I/O5I/O4I/O3I/O2I/O1I/O0R/BWEALECLECERERnBnFWEALECLEnFCEn

S3C2440A RISC MICROPROCESSOR NAND FLASH CONTROLLER6-11I/O15I/O

NAND FLASH CONTROLLER S3C2440A RISC MICROPROCESSOR6-12NAND FLASH CONFIGURATION REGISTERRegister Address R/W Description Reset ValueNFCONF 0x4E000000 R

S3C2440A RISC MICROPROCESSOR NAND FLASH CONTROLLER6-13CONTROL

NAND FLASH CONTROLLER S3C2440A RISC MICROPROCESSOR6-14CONTROL REGISTER (Continued)NFCONT Bit Description Initial StateSpareECCLock [6] Lock spare area

S3C2440A RISC MICROPROCESSOR NAND FLASH CONTROLLER6-15COMMAND

NAND FLASH CONTROLLER S3C2440A RISC MICROPROCESSOR6-16MAIN DATA AREA REGISTERRegister Address R/W Description Reset ValueNFMECCD0 0x4E000014 R/WNAND F

S3C2440A RISC MICROPROCESSOR NAND FLASH CONTROLLER6-17SPARE A

xxiv S3C2440A MICROCONTROLLERList of Figures (Continued)Figure Title PageNumber Number4-1 THUMB Instruction Set Formats ...

NAND FLASH CONTROLLER S3C2440A RISC MICROPROCESSOR6-18NFCON STATUS REGISTERRegister Address R/W Description Reset ValueNFSTAT 0x4E000020 R/W NAND flas

S3C2440A RISC MICROPROCESSOR NAND FLASH CONTROLLER6-19ECC0/1 S

NAND FLASH CONTROLLER S3C2440A RISC MICROPROCESSOR6-20MAIN DATA AREA ECC0 STATUS REGISTERRegister Address R/W Description Reset ValueNFMECC0 0x4E00002

S3C2440A RISC MICROPROCESSOR NAND FLASH CONTROLLER6-21BLOCK AD

NAND FLASH CONTROLLER S3C2440A RISC MICROPROCESSOR6-22The NFSLK and NFEBLK can be changed while Soft lock bit(NFCONT[12]) is enabled. But cannot be ch

S3C2440A RISC MICROPROCESSOR CLOCK & POWER MANAGEMENT7-17 CLOCK & POWER MANAGEMENTOVERVIEWThe Clock & Power management blo

CLOCK & POWER MANAGEMENT S3C2440A RISC MICROPROCESSOR7-2FUNCTIONAL DESCRIPTIONCLOCK ARCHITECTUREFigure 7-1 shows a block diagram of the clock arc

S3C2440A RISC MICROPROCESSOR CLOCK & POWER MANAGEMENT7-3Nand FlashControllerOSCMPLLUPLLCLKCNTLFCLKHDIVN PDIVNMpllControlSignalUpl

CLOCK & POWER MANAGEMENT S3C2440A RISC MICROPROCESSOR7-4PHASE LOCKED LOOP (PLL)The MPLL within the clock generator, as a circuit, synchronizes an

S3C2440A RISC MICROPROCESSOR CLOCK & POWER MANAGEMENT7-5DividerPLoop FilterFinM[7:0]S[1:0]PFDDividerMP[5:0]FvcoPUMPVCODividerSFre

S3C2440A MICROCONTROLLER xxvList of Figures (Continued)Figure Title PageNumber Number6-1 NAND Flash Controller Block Diagram...

CLOCK & POWER MANAGEMENT S3C2440A RISC MICROPROCESSOR7-6CLOCK CONTROL LOGICThe Clock Control Logic determines the clock source to be used, i.e.,

S3C2440A RISC MICROPROCESSOR CLOCK & POWER MANAGEMENT7-7Change PLL Settings In Normal Operation ModeDuring the operation of the S

CLOCK & POWER MANAGEMENT S3C2440A RISC MICROPROCESSOR7-8FCLK, HCLK, and PCLKFCLK is used by ARM920T.HCLK is used for AHB bus, which is used by th

S3C2440A RISC MICROPROCESSOR CLOCK & POWER MANAGEMENT7-9NOTES1. CLKDIVN should be set carefully not to exceed the limit of HCLK a

CLOCK & POWER MANAGEMENT S3C2440A RISC MICROPROCESSOR7-10POWER MANAGEMENTThe Power Management block controls the system clocks by software for th

S3C2440A RISC MICROPROCESSOR CLOCK & POWER MANAGEMENT7-11IDLESLEEPNORMAL(SLOW_BIT=0)SLOW(SLOW_BIT=1)IDLE_BIT=1Interrupts, EINT[0:

CLOCK & POWER MANAGEMENT S3C2440A RISC MICROPROCESSOR7-12NORMAL ModeIn Normal mode, all peripherals and the basic blocks including power manageme

S3C2440A RISC MICROPROCESSOR CLOCK & POWER MANAGEMENT7-13Users can change the frequency by enabling SLOW mode bit in CLKSLOW regi

CLOCK & POWER MANAGEMENT S3C2440A RISC MICROPROCESSOR7-14If the user switches from SLOW mode to Normal mode by disabling SLOW_BIT and MPLL_OFF bi

S3C2440A RISC MICROPROCESSOR CLOCK & POWER MANAGEMENT7-15SLEEP ModeThe block disconnects the internal power. So, there occurs no

xxvi S3C2440A MICROCONTROLLERList of Figures (Continued)Figure Title PageNumber Number11-1 UART Block Diagram (with FIFO)...

CLOCK & POWER MANAGEMENT S3C2440A RISC MICROPROCESSOR7-16Follow the Procedure to Wake-up from SLEEP mode1. The internal reset signal will be asse

S3C2440A RISC MICROPROCESSOR CLOCK & POWER MANAGEMENT7-17Power Control of VDDi and VDDiarmIn SLEEP mode, VDDi, VDDiarm, VDDMPLL a

CLOCK & POWER MANAGEMENT S3C2440A RISC MICROPROCESSOR7-18Signaling EINT[15:0] for WakeupThe S3C2440A can be woken up from SLEEP mode only if the

S3C2440A RISC MICROPROCESSOR CLOCK & POWER MANAGEMENT7-19Output Port State and SLEEP ModeThe output port should have a proper log

CLOCK & POWER MANAGEMENT S3C2440A RISC MICROPROCESSOR7-20CLOCK GENERATOR & POWER MANAGEMENT SPECIAL REGISTERLOCK TIME COUNT REGISTER (LOCKTIM

S3C2440A RISC MICROPROCESSOR CLOCK & POWER MANAGEMENT7-21PLL CONTROL REGISTER (MPLLCON & UPLLCON)Register Address R/W Descrip

CLOCK & POWER MANAGEMENT S3C2440A RISC MICROPROCESSOR7-22CLOCK CONTROL REGISTER (CLKCON)Register Address R/W Description Reset ValueCLKCON 0x4C00

S3C2440A RISC MICROPROCESSOR CLOCK & POWER MANAGEMENT7-23CLOCK SLOW CONTROL (CLKSLOW) REGISTERRegister Address R/W Description Re

CLOCK & POWER MANAGEMENT S3C2440A RISC MICROPROCESSOR7-24CLOCK DIVIDER CONTROL (CLKDIVN) REGISTERRegister Address R/W Description Reset ValueCLKD

S3C2440A RISC MICROPROCESSOR CLOCK & POWER MANAGEMENT7-25CAMERA CLOCK DIVIDER (CAMDIVN) REGISTERRegister Address R/W Description

S3C2440A MICROCONTROLLER xxviiList of Figures (Continued)Figure Title PageNumber Number21-1 IIS-Bus Block Diagram...

S3C2440A RISC MICROPROCESSOR

DMA S3C2440A RISC MICROPROCESSOR8-2DMA REQUEST SOURCESEach channel of the DMA controller can select one of the DMA request source among four DMA sour

S3C2440A RISC MICROPROCESSOR

DMA S3C2440A RISC MICROPROCESSOR8-4Demand/Handshake Mode ComparisonDemand and Handshake modes are related to the protocol between XnXDREQ and XnXDACK

S3C2440A RISC MICROPROCESSOR

DMA S3C2440A RISC MICROPROCESSOR8-6EXAMPLESSingle service in Demand Mode with Unit Transfer SizeThe assertion of XnXDREQ will be a need for every uni

S3C2440A RISC MICROPROCESSOR

DMA S3C2440A RISC MICROPROCESSOR8-8DMA INITIAL DESTINATION (DIDST) REGISTERRegister Address R/W Description Reset ValueDIDST0 0x4B000008 R/W DMA 0 in

S3C2440A RISC MICROPROCESSOR

DMA S3C2440A RISC MICROPROCESSOR8-10DMA CONTROL (DCON) REGISTER (Continued)DCONn Bit Description Initial StateSERVMODE [27] Select the service mode b

xxviii S3C2440A MICROCONTROLLERList of Figures (Continued)Figure Title PageNumber Number27-11 External Bus Request in ROM/SRAM Cycle(Tacs=0, Tcos=0,

S3C2440A RISC MICROPROCESSOR

DMA S3C2440A RISC MICROPROCESSOR8-12DMA STATUS (DSTAT) REGISTERRegister Address R/W Description Reset ValueDSTAT0 0x4B000014 R DMA 0 count register 0

S3C2440A RISC MICROPROCESSOR

DMA S3C2440A RISC MICROPROCESSOR8-14DMA MASK TRIGGER (DMASKTRIG) REGISTERRegister Address R/W Description Reset ValueDMASKTRIG0 0x4B000020 R/W DMA 0

S3C2440A RISC MICROPROCESSOR I/O PORTS9-19 I/O PORTSOVERVIEWS3C2440A has 130 multi-functional input/output port pins and there are eight ports as sho

I/O PORTS S3C2440A RISC MICROPROCESSOR9-2Table 9-1. S3C2440A Port Configuration (Sheet 1 of 5)Port A Selectable Pin FunctionsGPA22 Output only nFCE –

S3C2440A RISC MICROPROCESSOR I/O PORTS9-3Table 9-1. S3C2440A Port Configuration (Sheet 2 of 5) (Continued)Port B Selectable Pin FunctionsGPB10 Input/

I/O PORTS S3C2440A RISC MICROPROCESSOR9-4Table 9-1. S3C2440A Port Configuration (Sheet 3 of 5) (Continued)Port D Selectable Pin FunctionsGPD15 Input/

S3C2440A RISC MICROPROCESSOR I/O PORTS9-5Table 9-1. S3C2440A Port Configuration (Sheet 4 of 5) (Continued)Port F Selectable Pin FunctionsGPF7 Input/o

I/O PORTS S3C2440A RISC MICROPROCESSOR9-6Table 9-1. S3C2440A Port Configuration (Sheet 5 of 5) (Continued)Port H Selectable Pin FunctionsGPH10 Input/

S3C2440A MICROCONTROLLER xxixList of TablesTable Title PageNumber Number1-1 289-Pin FBGA Pin Assignments – Pin Number Order (Sheet 1 of 3)...

S3C2440A RISC MICROPROCESSOR I/O PORTS9-7PORT CONTROL DESCRIPTIONSPORT CONFIGURATION REGISTER (GPACON-GPJCON)In S3C2440A, most of the pins are multip

I/O PORTS S3C2440A RISC MICROPROCESSOR9-8I/O PORT CONTROL REGISTERPORT A CONTROL REGISTERS (GPACON, GPADAT)Register Address R/W Description Reset Val

S3C2440A RISC MICROPROCESSOR I/O PORTS9-9

I/O PORTS S3C2440A RISC MICROPROCESSOR9-10PORT A CONTROL REGISTERS (GPACON, GPADAT) (Continued)GPADAT Bit DescriptionGPA[24:0] [24:0] When the port i

S3C2440A RISC MICROPROCESSOR I/O PORTS9-11 PORT B CONTROL REGISTERS (GPBCON, GPBDAT, GPBUP)Register Address R/W Description Reset ValueGPBCON 0x56000

I/O PORTS S3C2440A RISC MICROPROCESSOR9-12PORT C CONTROL REGISTERS (GPCCON, GPCDAT, GPCUP)Register Address R/W Description Reset ValueGPCCON 0x560000

S3C2440A RISC MICROPROCESSOR I/O PORTS9-13PORT C CONTROL REGISTERS (GPCCON, GPCDAT, GPCUP) (Continued)GPCDAT Bit DescriptionGPC[15:0] [15:0] When the

I/O PORTS S3C2440A RISC MICROPROCESSOR9-14PORT D CONTROL REGISTERS (GPDCON, GPDDAT, GPDUP)Register Address R/W Description Reset ValueGPDCON 0x560000

S3C2440A RISC MICROPROCESSOR I/O PORTS9-15PORT D CONTROL REGISTERS (GPDCON, GPDDAT, GPDUP) (Continued)GPDDAT Bit DescriptionGPD[15:0] [15:0] When the

I/O PORTS S3C2440A RISC MICROPROCESSOR9-16PORT E CONTROL REGISTERS (GPECON, GPEDAT, GPEUP)Register Address R/W Description Reset ValueGPECON 0x560000

xxx S3C2440A MICROCONTROLLERList of Tables (Continued)Table Title PageNumber Number8-1 DMA Request Sources for Each Channel...

S3C2440A RISC MICROPROCESSOR I/O PORTS9-17PORT E CONTROL REGISTERS (GPECON, GPEDAT, GPEUP) (Continued)GPEDAT Bit DescriptionGPE[15:0] [15:0] When the

I/O PORTS S3C2440A RISC MICROPROCESSOR9-18PORT F CONTROL REGISTERS (GPFCON, GPFDAT)If GPF0–GPF7 will be used for wake-up signals at power down mode,

S3C2440A RISC MICROPROCESSOR I/O PORTS9-19PORT G CONTROL REGISTERS (GPGCON, GPGDAT)If GPG0–GPG7 will be used for wake-up signals at Sleep mode, the p

I/O PORTS S3C2440A RISC MICROPROCESSOR9-20PORT G CONTROL REGISTERS (GPGCON, GPGDAT) (Continued)GPGDAT Bit DescriptionGPG[15:0] [15:0] When the port i

S3C2440A RISC MICROPROCESSOR I/O PORTS9-21PORT H CONTROL REGISTERS (GPHCON, GPHDAT)Register Address R/W Description Reset ValueGPHCON 0x56000070 R/W

I/O PORTS S3C2440A RISC MICROPROCESSOR9-22PORT J CONTROL REGISTERS (GPJCON, GPJDAT)Register Address R/W Description Reset ValueGPJCON 0x560000d0 R/W

S3C2440A RISC MICROPROCESSOR I/O PORTS9-23PORT J CONTROL REGISTERS (GPJCON, GPJDAT) (Continued)GPJDAT Bit DescriptionGPJ15:0] [12:0] When the port is

I/O PORTS S3C2440A RISC MICROPROCESSOR9-24MISCELLANEOUS CONTROL REGISTER (MISCCR)In Sleep mode, the data bus(D[31:0] or D[15:0] can be set as Hi-Z an

S3C2440A RISC MICROPROCESSOR I/O PORTS9-25MISCELLANEOUS CONTROL REGISTER (MISCCR) (Continued)MISCCR Bit Description Reset ValueCLKSEL1 (Note)[10:8] S

I/O PORTS S3C2440A RISC MICROPROCESSOR9-26DCLK CONTROL REGISTERS (DCLKCON)Register Address R/W Description Reset ValueDCLKCON 0x56000084 R/W DCLK0/1

S3C2440A MICROCONTROLLER iiiTable of ContentsChapter 1 Product OverviewIntroduction...

S3C2440A RISC MICROPROCESSOR PRODUCT OVERVIEW1-11 PRODUCT OVERVIEWINTRODUCTIONThis user’s manual describes SAMSUNG&a

S3C2440A RISC MICROPROCESSOR I/O PORTS9-27EXTINTn (External Interrupt Control Register n)The 8 external interrupts can be requested by various signa

I/O PORTS S3C2440A RISC MICROPROCESSOR9-28EXTINTn (External Interrupt Control Register n) (Continued)EXTINT1 Bit DescriptionFLTEN15 [31] Filter enab

S3C2440A RISC MICROPROCESSOR I/O PORTS9-29EXTINTn (External Interrupt Control Register n) (Continued)EXTINT2 Bit Description Reset ValueFLTEN23 [31]

I/O PORTS S3C2440A RISC MICROPROCESSOR9-30EXTINTn (External Interrupt Control Register n) (Continued)EXTINT2 Bit Description Reset ValueFLTEN17 [7]

S3C2440A RISC MICROPROCESSOR I/O PORTS9-31EINTFLTn (External Interrupt Filter Register n)To recognize the level interrupt, the valid logic level on

I/O PORTS S3C2440A RISC MICROPROCESSOR9-32EINTMASK (External Interrupt Mask Register)Register Address R/W Description Reset ValueEINTMASK 0x560000a4

S3C2440A RISC MICROPROCESSOR I/O PORTS9-33EINTPEND (External Interrupt Pending Register)Register Address R/W Description Reset ValueEINTPEND 0x560000

I/O PORTS S3C2440A RISC MICROPROCESSOR9-34

S3C2440A RISC MICROPROCESSOR I/O PORTS9-35GSTATUSn (General Status Registers)Register Address R/W Description Reset ValueGSTATUS0 0x560000ac R Extern

I/O PORTS S3C2440A RISC MICROPROCESSOR9-36DSCn (Drive Strength Control)Control the Memory I/O drive strengthRegister Address R/W Description Reset Va

PRODUCT OVERVIEW S3C2440A RISC MICROPROCESSOR1-2 FEATURESArchitecture• Integrated system for hand-held devices andgeneral embedded applications.• 16

S3C2440A RISC MICROPROCESSOR I/O PORTS9-37DSCn (Drive Strength Control)DSC1 Bit Description Reset ValueDSC_SCK1 [29:28] SCLK1 drive strength.00: 12mA

I/O PORTS S3C2440A RISC MICROPROCESSOR9-38MSLCON (Memory Sleep Control Register)Select memory interface status when in SLEEP mode.Register Address R/

S3C2440A RISC MICROPROCESSOR PWM TIMER10-110 PWM TIMEROVERVIEWThe S3C2440A has five 16-bit timers. Timer 0, 1

PWM TIMER S3C2440A RISC MICROPROCESSOR10-2ClockDivider5:1 MUXDead ZoneGeneratorTOUT0TOUT1TOUT2ControlLogic0TCMPB0 TCNTB0ControlLogic1TCMPB1 TCNTB15:1

S3C2440A RISC MICROPROCESSOR PWM TIMER10-3PWM TIMER OPERATIONPRESCALER & DIVIDERAn 8-bit prescaler and a

PWM TIMER S3C2440A RISC MICROPROCESSOR10-4AUTO RELOAD & DOUBLE BUFFERINGS3C2440A PWM Timers have a double buffering function, enabling the reload

S3C2440A RISC MICROPROCESSOR PWM TIMER10-5TIMER INITIALIZATION USING MANUAL UPDATE BIT AND INVERTER BITAn aut

PWM TIMER S3C2440A RISC MICROPROCESSOR10-6TIMER OPERATIONTOUTn1 2 4 650 110 4040 60203 7 9 105 8 11Figure 10-4. Example of a Timer OperationThe above

S3C2440A RISC MICROPROCESSOR PWM TIMER10-7PULSE WIDTH MODULATION (PWM)WriteTCMPBn = 60WriteTCMPBn = 50WriteTC

PWM TIMER S3C2440A RISC MICROPROCESSOR10-8OUTPUT LEVEL CONTROLInverter offInitial State Period 1 Period 2 Timer StopInverter onFigure 10-6. Inverter O

S3C2440A RISC MICROPROCESSOR PRODUCT OVERVIEW1-3FEATURES (Continued)Interrupt Controller• 60 Interrupt sources(One Watch dog timer, 5 timers, 9 UART

S3C2440A RISC MICROPROCESSOR PWM TIMER10-9DEAD ZONE GENERATORThe Dead Zone is for the PWM control in a power

PWM TIMER S3C2440A RISC MICROPROCESSOR10-10DMA REQUEST MODEThe PWM timer can generate a DMA request at every specific time. The timer keeps DMA reques

S3C2440A RISC MICROPROCESSOR PWM TIMER10-11PWM TIMER CONTROL REGISTERSTIMER CONFIGURATION REGISTER0 (TCFG0)Ti

PWM TIMER S3C2440A RISC MICROPROCESSOR10-12TIMER CONFIGURATION REGISTER1 (TCFG1)Register Address R/W Description Reset ValueTCFG1 0x51000004 R/W 5-MUX

S3C2440A RISC MICROPROCESSOR PWM TIMER10-13TIMER CONTROL (TCON) REGISTERRegister Address R/W Description Rese

PWM TIMER S3C2440A RISC MICROPROCESSOR10-14TIMER CONTROL (TCON) REGISTER (Continued)TCON Bit Description Initial stateReserved [7:5] ReservedDead zone

S3C2440A RISC MICROPROCESSOR PWM TIMER10-15TIMER 0 COUNT BUFFER REGISTER & COMPARE BUFFER REGISTER (TCNTB

PWM TIMER S3C2440A RISC MICROPROCESSOR10-16TIMER 1 COUNT BUFFER REGISTER & COMPARE BUFFER REGISTER (TCNTB1/TCMPB1)Register Address R/W Description

S3C2440A RISC MICROPROCESSOR PWM TIMER10-17TIMER 2 COUNT BUFFER REGISTER & COMPARE BUFFER REGISTER (TCNTB

PWM TIMER S3C2440A RISC MICROPROCESSOR10-18TIMER 3 COUNT BUFFER REGISTER & COMPARE BUFFER REGISTER (TCNTB3/TCMPB3)Register Address R/W Description

PRODUCT OVERVIEW S3C2440A RISC MICROPROCESSOR1-4 FEATURES (Continued)A/D Converter & Touch Screen Interface• 8-ch multiplexed ADC• Max. 500KSPS

S3C2440A RISC MICROPROCESSOR PWM TIMER10-19TIMER 4 COUNT BUFFER REGISTER (TCNTB4)Register Address R/W Descrip

PWM TIMER S3C2440A RISC MICROPROCESSOR10-20NOTES

S3C2440A RISC MICROPROCESSOR UART11-111 UARTOVERVIEWThe S3C2440A Universal Asynchronous Receiver and Trans

UART S3C2440A RISC MICROPROCESSOR11-2BLOCK DIAGRAMBuad-rateGeneratorControlUnitTransmitterReceiverPeripheral BUSTXDnClock Source(PCLK, FCLK/n,UEXTCLK

S3C2440A RISC MICROPROCESSOR UART11-3UART OPERATIONThe following sections describe the UART operations tha

UART S3C2440A RISC MICROPROCESSOR11-4Auto Flow Control (AFC)The S3C2440A's UART 0 and UART 1 support auto flow control with nRTS and nCTS signal

S3C2440A RISC MICROPROCESSOR UART11-5RS-232C interfaceIf the user wants to connect the UART to modem inter

UART S3C2440A RISC MICROPROCESSOR11-6UART Error Status FIFOUART has the error status FIFO besides the Rx FIFO register. The error status FIFO indicat

S3C2440A RISC MICROPROCESSOR UART11-7Baud-rate GenerationEach UART's baud-rate generator provides the

UART S3C2440A RISC MICROPROCESSOR11-8Infrared (IR) ModeThe S3C2440A UART block supports infrared (IR) transmission and reception, which can be select

S3C2440A RISC MICROPROCESSOR PRODUCT OVERVIEW1-5BLOCK DIAGRAMARM920TARM9TDMIProcessor core(Internal Embedded ICE)DD[31:0]WriteBackPA TagRAMDataMMUC13

S3C2440A RISC MICROPROCESSOR UART11-9StartBitStopBitData BitsSIO Frame0 1 0 1 0 0 1 1 0 1Figure 11-5. Seri

UART S3C2440A RISC MICROPROCESSOR11-10UART SPECIAL REGISTERSUART LINE CONTROL REGISTERThere are three UART line control registers including ULCON0, U

S3C2440A RISC MICROPROCESSOR UART11-11UART CONTROL REGISTERThere are three UART control registers includin

UART S3C2440A RISC MICROPROCESSOR11-12UART CONTROL REGISTER (Continued)UCONn Bit Description Initial StateTx Interrupt Type [9] Interrupt request typ

S3C2440A RISC MICROPROCESSOR UART11-13UART CONTROL REGISTER (Continued)UCONn Bit Description Initial State

UART S3C2440A RISC MICROPROCESSOR11-14UART FIFO CONTROL REGISTERThere are three UART FIFO control registers including UFCON0, UFCON1 and UFCON2 in th

S3C2440A RISC MICROPROCESSOR UART11-15UART MODEM CONTROL REGISTERThere are two UART MODEM control register

UART S3C2440A RISC MICROPROCESSOR11-16UART TX/RX STATUS REGISTERThere are three UART Tx/Rx status registers including UTRSTAT0, UTRSTAT1 and UTRSTAT2

S3C2440A RISC MICROPROCESSOR UART11-17UART ERROR STATUS REGISTERThere are three UART Rx error status regis

UART S3C2440A RISC MICROPROCESSOR11-18UART FIFO STATUS REGISTERThere are three UART FIFO status registers including UFSTAT0, UFSTAT1 and UFSTAT2 in t

PRODUCT OVERVIEW S3C2440A RISC MICROPROCESSOR1-6 PIN ASSIGNMENTSBOTTOM VIEWUTRPNMLKJHGFEDCBA1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17Figure 1-2. S3C24

S3C2440A RISC MICROPROCESSOR UART11-19UART MODEM STATUS REGISTERThere are two UART modem status registers

UART S3C2440A RISC MICROPROCESSOR11-20UART TRANSMIT BUFFER REGISTER (HOLDING REGISTER & FIFO REGISTER)There are three UART transmit buffer regist

S3C2440A RISC MICROPROCESSOR UART11-21UART BAUD RATE DIVISOR REGISTERThere are three UART baud rate diviso

UART S3C2440A RISC MICROPROCESSOR11-22NOTES

S3C2440A RISC MICROPROCESSOR USB HOST12-112 USB HOST CONTROLLEROVERVIEWS3C2440A supports 2-port USB host inter

USB HOST S3C2440A RISC MICROPROCESSOR12-2USB HOST CONTROLLER SPECIAL REGISTERSThe S3C2440A USB host controller complies with OHCI Rev 1.0. Refer to O

S3C2440A RISC MICROPROCESSOR USB DEVICE13-113 USB DEVICE CONTROLLEROVERVIEWUniversal Serial Bus (USB) devi

USB DEVICE S3C2440A RISC MICROPROCESSOR13-2SIERT_VP_OUTRT_VM_INRT_VP_INRXDRT_UXSUSPENDRT_UX_OENRT_VM_OUTMC_ADDR[13:0]SIUGFIFIFOsMCU&DMAI/FMC_DATA

S3C2440A RISC MICROPROCESSOR USB DEVICE13-3USB DEVICE CONTROLLER SPECIAL REGISTERSThis section describes d

USB DEVICE S3C2440A RISC MICROPROCESSOR13-4USB DEVICE CONTROLLER SPECIAL REGISTERS (Continued)Register Name Description Offset AddressEP2_DMA_UNIT En

S3C2440A RISC MICROPROCESSOR PRODUCT OVERVIEW1-7Table 1-1. 289-Pin FBGA Pin Assignments – Pin Number Order (Sheet 1 of 3)PinNumberPin Name PinNumberP

S3C2440A RISC MICROPROCESSOR USB DEVICE13-5FUNCTION ADDRESS REGISTER (FUNC_ADDR_REG)This register maintain

USB DEVICE S3C2440A RISC MICROPROCESSOR13-6POWER MANAGEMENT REGISTER (PWR_REG)This register acts as a power control register in the USB block.Registe

S3C2440A RISC MICROPROCESSOR USB DEVICE13-7INTERRUPT REGISTER (EP_INT_REG/USB_INT_REG)The USB core has two

USB DEVICE S3C2440A RISC MICROPROCESSOR13-8INTERRUPT REGISTER (EP_INT_REG/USB_INT_REG) (Continued)Register Address R/W Description Reset ValueUSB_INT

S3C2440A RISC MICROPROCESSOR USB DEVICE13-9INTERRUPT ENABLE REGISTER (EP_INT_EN_REG/USB_INT_EN_REG)Corresp

USB DEVICE S3C2440A RISC MICROPROCESSOR13-10FRAME NUMBER REGISTER (FPAME_NUM1_REG/FRAME_NUM2_REG)When the host transfers USB packets, each Start Of F

S3C2440A RISC MICROPROCESSOR USB DEVICE13-11INDEX REGISTER (INDEX_REG)The INDEX register is used to indica

USB DEVICE S3C2440A RISC MICROPROCESSOR13-12END POINT0 CONTROL STATUS REGISTER (EP0_CSR)This register has the control and status bits for Endpoint 0.

S3C2440A RISC MICROPROCESSOR USB DEVICE13-13END POINT IN CONTROL STATUS REGISTER (IN_CSR1_REG/IN_CSR2_REG)

USB DEVICE S3C2440A RISC MICROPROCESSOR13-14END POINT IN CONTROL STATUS REGISTER (IN_CSR1_REG/IN_CSR2_REG) (Continued)Register Address R/W Descriptio

PRODUCT OVERVIEW S3C2440A RISC MICROPROCESSOR1-8 Table 1-1. 289-Pin FBGA Pin Assignments – Pin Number Order (Sheet 2 of 3) (Continued)PinNumberPin Nam

S3C2440A RISC MICROPROCESSOR USB DEVICE13-15END POINT OUT CONTROL STATUS REGISTER (OUT_CSR1_REG/OUT_CSR2_R

USB DEVICE S3C2440A RISC MICROPROCESSOR13-16END POINT OUT CONTROL STATUS REGISTER (OUT_CSR1_REG/OUT_CSR2_REG) (Continued)Register Address R/W Descrip

S3C2440A RISC MICROPROCESSOR USB DEVICE13-17END POINT OUT WRITE COUNT REGISTER (OUT_FIFO_CNT1_REG/OUT_FIFO

USB DEVICE S3C2440A RISC MICROPROCESSOR13-18DMA INTERFACE CONTROL REGISTER (EPN_DMA_CON)Register Address R/W Description Reset ValueEP1_DMA_CON 0x520

S3C2440A RISC MICROPROCESSOR USB DEVICE13-19DMA UNIT COUNTER REGISTER (EPN_DMA_UNIT)This register is valid

USB DEVICE S3C2440A RISC MICROPROCESSOR13-20DMA FIFO COUNTER REGISTER (EPN_DMA_FIFO)This register has values in byte size in FIFO to be transferred b

S3C2440A RISC MICROPROCESSOR USB DEVICE13-21DMA TOTAL TRANSFER COUNTER REGISTER (EPn_DMA_TTC_L,M,H)This re

USB DEVICE S3C2440A RISC MICROPROCESSOR13-22NOTES

S3C2440A RISC MICROPROCESSOR INTERRUPT CONTROLLER14-114 INTERRUPT CONTROLLEROVERVIEWThe interrupt controll

INTERRUPT CONTROLLER S3C2440A RISC MICROPROCESSOR14-2INTERRUPT CONTROLLER OPERATIONF-bit and I-bit of Program Status Register (PSR)If the F-bit of PS

S3C2440A RISC MICROPROCESSOR PRODUCT OVERVIEW1-9Table 1-1. 289-Pin FBGA Pin Assignments – Pin Number Order (Sheet 3 of 3) (Continued)PinNumberPin Nam

S3C2440A RISC MICROPROCESSOR INTERRUPT CONTROLLER14-3INTERRUPT SOURCESThe interrupt controller supports 60

INTERRUPT CONTROLLER S3C2440A RISC MICROPROCESSOR14-4INTERRUPT SUB SOURCESSub Sources Descriptions SourceINT_AC97 AC97 interrupt INT_WDT_AC97INT_WDT

S3C2440A RISC MICROPROCESSOR INTERRUPT CONTROLLER14-5INTERRUPT PRIORITY GENERATING BLOCKThe priority logic

INTERRUPT CONTROLLER S3C2440A RISC MICROPROCESSOR14-6INTERRUPT PRIORITYEach arbiter can handle six interrupt requests based on the one bit arbiter mo

S3C2440A RISC MICROPROCESSOR INTERRUPT CONTROLLER14-7INTERRUPT CONTROLLER SPECIAL REGISTERSThere are five

INTERRUPT CONTROLLER S3C2440A RISC MICROPROCESSOR14-8SOURCE PENDING (SRCPND) REGISTER (Continued)SRCPND Bit Description Initial StateINT_ADC [31] 0 =

S3C2440A RISC MICROPROCESSOR INTERRUPT CONTROLLER14-9INTERRUPT MODE (INTMOD) REGISTERThis register is comp

INTERRUPT CONTROLLER S3C2440A RISC MICROPROCESSOR14-10INTERRUPT MODE (INTMOD) REGISTER (Continued)INTMOD Bit Description Initial StateINT_ADC [31] 0

S3C2440A RISC MICROPROCESSOR INTERRUPT CONTROLLER14-11INTERRUPT MASK (INTMSK) REGISTERThis register also h

INTERRUPT CONTROLLER S3C2440A RISC MICROPROCESSOR14-12INTERRUPT MASK (INTMSK) REGISTER (Continued)INTMSK Bit Description Initial StateINT_ADC [31] 0

PRODUCT OVERVIEW S3C2440A RISC MICROPROCESSOR1-10 Table 1-2. S3C2440A 289-Pin FBGA Pin Assignments (Sheet 1 of 9)PinNumberPinNameDefaultFunctionI/O St

S3C2440A RISC MICROPROCESSOR INTERRUPT CONTROLLER14-13PRIORITY REGISTER (PRIORITY)Register Address R/W Des

INTERRUPT CONTROLLER S3C2440A RISC MICROPROCESSOR14-14INTERRUPT PENDING (INTPND) REGISTEREach of the 32 bits in the interrupt pending register shows

S3C2440A RISC MICROPROCESSOR INTERRUPT CONTROLLER14-15INTERRUPT PENDING (INTPND) REGISTER (Continued)INTPN

INTERRUPT CONTROLLER S3C2440A RISC MICROPROCESSOR14-16INTERRUPT OFFSET (INTOFFSET) REGISTERThe value in the interrupt offset register shows which int

S3C2440A RISC MICROPROCESSOR INTERRUPT CONTROLLER14-17SUB SOURCE PENDING (SUBSRCPND) REGISTERYou can clear

INTERRUPT CONTROLLER S3C2440A RISC MICROPROCESSOR14-18INTERRUPT SUB MASK (INTSUBMSK) REGISTERThis register has 11 bits each of which is related to an

S3C2440A RISC MICROPROCESSOR LCD CONTROLLER15-115 LCD CONTROLLEROVERVIEWThe LCD controller in the S3C244

LCD CONTROLLER S3C2440A RISC MICROPROCESSOR15-2COMMON FEATURESThe LCD controller has a dedicated DMA that supports to fetch the image data from vi

S3C2440A RISC MICROPROCESSOR LCD CONTROLLER15-3BLOCK DIAGRAMSystem BusLPC3600 is a timing control logic

LCD CONTROLLER S3C2440A RISC MICROPROCESSOR15-4STN LCD CONTROLLER OPERATIONTIMING GENERATOR (TIMEGEN)The TIMEGEN generates the control signals for

iv S3C2440A MICROCONTROLLERTable of Contents (Continued)Chapter 3 ARM Instruction SetInstruction Set Summay...

S3C2440A RISC MICROPROCESSOR PRODUCT OVERVIEW1-11Table 1-2. S3C2440A 289-Pin FBGA Pin Assignments (Sheet 2 of 9) (Continued)PinNumberPinNameDefaultFu

S3C2440A RISC MICROPROCESSOR LCD CONTROLLER15-5Table 15-1. Relation Between VCLK and CLKVAL (STN, HCLK

LCD CONTROLLER S3C2440A RISC MICROPROCESSOR15-6256 Level Color Mode OperationThe S3C2440A LCD controller can support an 8-bit per pixel 256 color

S3C2440A RISC MICROPROCESSOR LCD CONTROLLER15-7DITHERING AND FRAME RATE CONTROLIn case of STN LCD displa

LCD CONTROLLER S3C2440A RISC MICROPROCESSOR15-8Display TypesThe LCD controller supports 3 types of LCD drivers: 4-bit dual scan, 4-bit single scan

S3C2440A RISC MICROPROCESSOR LCD CONTROLLER15-9MEMORY DATA FORMAT (STN, BSWP = 0)Mono 4-bit Dual Scan Di

LCD CONTROLLER S3C2440A RISC MICROPROCESSOR15-10MEMORY DATA FORMAT ( STN, BSWP=0 ) (CONTINUED)In 4-level gray mode, 2 bits of video data correspon

S3C2440A RISC MICROPROCESSOR LCD CONTROLLER15-1116 BPP color mode16 bits (5 bits of red, 6 bits of green

LCD CONTROLLER S3C2440A RISC MICROPROCESSOR15-124-bit Dual Scan Display4-bit Single Scan Display8-bit Single Scan Display. . . . .

S3C2440A RISC MICROPROCESSOR LCD CONTROLLER15-13VD3R1VD2G1VD1B1VD0R2VD3G2VD2B2VD1R3VD0G3...1 Pixel...

LCD CONTROLLER S3C2440A RISC MICROPROCESSOR15-14Timing RequirementsImage data should be transferred from the memory to the LCD driver using the VD

PRODUCT OVERVIEW S3C2440A RISC MICROPROCESSOR1-12 Table 1-2. S3C2440A 289-Pin FBGA Pin Assignments (Sheet 3 of 9) (Continued)PinNumberPinNameDefaultFu

S3C2440A RISC MICROPROCESSOR LCD CONTROLLER15-15WDLYWLHLINE1LINE2LINE3LINE4LINE5LINE6 LINE1LINEnFirst Li

LCD CONTROLLER S3C2440A RISC MICROPROCESSOR15-16TFT LCD CONTROLLER OPERATIONThe TIMEGEN generates the control signals for LCD driver, such as VSYN

S3C2440A RISC MICROPROCESSOR LCD CONTROLLER15-17 MEMORY DATA FORMAT (TFT)This section includes some exam

LCD CONTROLLER S3C2440A RISC MICROPROCESSOR15-1816BPP Display(BSWP = 0, HWSWP = 0)D[31:16] D[15:0]000H P1 P2004H P3 P4008H P5 P6...(BSWP = 0, HWSW

S3C2440A RISC MICROPROCESSOR LCD CONTROLLER15-198BPP Display(BSWP = 0, HWSWP = 0)D[31:24] D[23:16] D[15:

LCD CONTROLLER S3C2440A RISC MICROPROCESSOR15-204BPP Display(BSWP = 0, HWSWP = 0)D[31:28] D[27:24] D[23:20] D[19:16] D[15:12] D[11:8] D[7:4] D[3:0

S3C2440A RISC MICROPROCESSOR LCD CONTROLLER15-21256 PALETTE USAGE (TFT)Palette Configuration and Format

LCD CONTROLLER S3C2440A RISC MICROPROCESSOR15-221 2 3 4 5LCD Panel16BPP 5:5:5+1 Format(Non-Palette)A[31] A[30] A[29] A[28] A[27] A[26]A[25] A[24]

S3C2440A RISC MICROPROCESSOR LCD CONTROLLER15-23INT_FrSynVSYNCHSYNCVDENHSYNCVCLKVDLENDVBPD+1VSPW+1VFPD+1

LCD CONTROLLER S3C2440A RISC MICROPROCESSOR15-24SAMSUNG TFT LCD PANEL (3.5” PORTRAIT / 256K COLOR / REFLECTIVE A-SI/TRANSFLECTIVE A-SI TFTLCD)The

S3C2440A RISC MICROPROCESSOR PRODUCT OVERVIEW1-13Table 1-2. S3C2440A 289-Pin FBGA Pin Assignments (Sheet 4 of 9) (Continued)PinNumberPinNameDefaultFu

S3C2440A RISC MICROPROCESSOR LCD CONTROLLER15-25VIRTUAL DISPLAY (TFT/STN)The S3C2440A supports hardware

LCD CONTROLLER S3C2440A RISC MICROPROCESSOR15-26LCD POWER ENABLE (STN/TFT)The S3C2440A provides Power enable (PWREN) function. When PWREN is set t

S3C2440A RISC MICROPROCESSOR LCD CONTROLLER15-27LCD CONTROLLER SPECIAL REGISTERSLCD Control 1 RegisterRe

LCD CONTROLLER S3C2440A RISC MICROPROCESSOR15-28LCD Control 2 RegisterRegister Address R/W Description Reset ValueLCDCON2 0X4D000004 R/W LCD contr

S3C2440A RISC MICROPROCESSOR LCD CONTROLLER15-29LCD Control 3 RegisterRegister Address R/W Description R

LCD CONTROLLER S3C2440A RISC MICROPROCESSOR15-30LCD Control 4 RegisterRegister Address R/W Description Reset ValueLCDCON4 0X4D00000C R/W LCD contr

S3C2440A RISC MICROPROCESSOR LCD CONTROLLER15-31LCD Control 5 RegisterRegister Address R/W Description R

LCD CONTROLLER S3C2440A RISC MICROPROCESSOR15-32LCD Control 5 Register (Continued)LCDCON5 Bit Description Initial stateINVVDEN [6] TFT: This bit i

S3C2440A RISC MICROPROCESSOR LCD CONTROLLER15-33FRAME BUFFER START ADDRESS 1 REGISTERRegister Address R/

LCD CONTROLLER S3C2440A RISC MICROPROCESSOR15-34FRAME Buffer Start Address 3 RegisterRegister Address R/W Description Reset ValueLCDSADDR3 0X4D000

PRODUCT OVERVIEW S3C2440A RISC MICROPROCESSOR1-14 Table 1-2. S3C2440A 289-Pin FBGA Pin Assignments (Sheet 5 of 9) (Continued)PinNumberPinNameDefaultFu

S3C2440A RISC MICROPROCESSOR LCD CONTROLLER15-35RED Lookup Table RegisterRegister Address R/W Descriptio

LCD CONTROLLER S3C2440A RISC MICROPROCESSOR15-36Dithering Mode RegisterRegister Address R/W Description Reset ValueDITHMODE 0X4D00004C R/W STN: Di

S3C2440A RISC MICROPROCESSOR LCD CONTROLLER15-37Temp Palette RegisterRegister Address R/W Description Re

LCD CONTROLLER S3C2440A RISC MICROPROCESSOR15-38LCD Interrupt Pending RegisterRegister Address R/W Description Reset ValueLCDINTPND 0X4D000054 R/W

S3C2440A RISC MICROPROCESSOR LCD CONTROLLER15-39LCD Interrupt Mask RegisterRegister Address R/W Descript

LCD CONTROLLER S3C2440A RISC MICROPROCESSOR15-40TCON Control RegisterRegister Address R/W Description Reset ValueTCONSEL 0X4D000060 R/W This regis

S3C2440A RISC MICROPROCESSOR LCD CONTROLLER15-41Register Setting Guide (STN)The LCD controller supports

LCD CONTROLLER S3C2440A RISC MICROPROCESSOR15-42Example 1:160 x 160, 4-level gray, 80 frame/sec, 4-bit single scan display, HCLK frequency is 60 M

S3C2440A RISC MICROPROCESSOR LCD CONTROLLER15-43Gray Level Selection GuideThe S3C2440A LCD controller ca

LCD CONTROLLER S3C2440A RISC MICROPROCESSOR15-44Register Setting Guide (TFT LCD)The CLKVAL register value determines the frequency of VCLK and fra

S3C2440A RISC MICROPROCESSOR PRODUCT OVERVIEW1-15Table 1-2. S3C2440A 289-Pin FBGA Pin Assignments (Sheet 6 of 9) (Continued)PinNumberPinNameDefaultFu

S3C2440A RISC MICROPROCESSOR ADC AND TOUCH SCREEN INTERFACE16-116 ADC & TOUCH SCREEN INTERFACEOVERVIEWThe 10-bit CMOS ADC (Analog to Digital Conv

ADC AND TOUCH SCREEN INTERFACE S3C2440A RISC MICROPROCESSOR16-2ADC & TOUCH SCREEN INTERFACE OPERATIONBLOCK DIAGRAMFigure 16-1 shows the functiona

S3C2440A RISC MICROPROCESSOR ADC AND TOUCH SCREEN INTERFACE16-3FUNCTION DESCRIPTIONSA/D Conversion TimeWhen the GCLK frequency is 50MHz and the presc

ADC AND TOUCH SCREEN INTERFACE S3C2440A RISC MICROPROCESSOR16-4Programming Notes1. The A/D converted data can be accessed by means of interrupt or po

S3C2440A RISC MICROPROCESSOR ADC AND TOUCH SCREEN INTERFACE16-5ADC AND TOUCH SCREEN INTERFACE SPECIAL REGISTERSADC CONTROL REGISTER (ADCCON)Register

ADC AND TOUCH SCREEN INTERFACE S3C2440A RISC MICROPROCESSOR16-6ADC TOUCH SCREEN CONTROL REGISTER (ADCTSC)Register Address R/W Description Reset Value

S3C2440A RISC MICROPROCESSOR ADC AND TOUCH SCREEN INTERFACE16-7ADC START DELAY REGISTER (ADCDLY)Register Address R/W Description Reset ValueADCDLY 0x

ADC AND TOUCH SCREEN INTERFACE S3C2440A RISC MICROPROCESSOR16-8ADC CONVERSION DATA REGISTER (ADCDAT0)Register Address R/W Description Reset ValueADCD

S3C2440A RISC MICROPROCESSOR ADC AND TOUCH SCREEN INTERFACE16-9ADC CONVERSION DATA REGISTER (ADCDAT1)Register Address R/W Description Reset ValueADCD

ADC AND TOUCH SCREEN INTERFACE S3C2440A RISC MICROPROCESSOR16-10NOTES

PRODUCT OVERVIEW S3C2440A RISC MICROPROCESSOR1-16 Table 1-2. S3C2440A 289-Pin FBGA Pin Assignments (Sheet 7 of 9) (Continued)PinNumberPinNameDefaultFu

S3C2440A RISC MICROPROCESSOR REAL TIME CLOCK17-117 REAL TIME CLOCK OVERVIEWThe Real Time Clock (RTC) unit

REAL TIME CLOCK S3C2440A RISC MICROPROCESSOR17-2REAL TIME CLOCK OPERATION215 Clock DividerXTOrtcXTIrtcControl RegisterSEC MIN HOUR DAY DATE MON YEARL

S3C2440A RISC MICROPROCESSOR REAL TIME CLOCK17-3ALARM FUNCTIONThe RTC generates an alarm signal at a spec

REAL TIME CLOCK S3C2440A RISC MICROPROCESSOR17-4REAL TIME CLOCK SPECIAL REGISTERSREAL TIME CLOCK CONTROL (RTCCON) REGISTERThe RTCCON register consist

S3C2440A RISC MICROPROCESSOR REAL TIME CLOCK17-5RTC ALARM CONTROL (RTCALM) REGISTERThe RTCALM register de

REAL TIME CLOCK S3C2440A RISC MICROPROCESSOR17-6ALARM SECOND DATA (ALMSEC) REGISTERRegister Address R/W Description Reset ValueALMSEC 0x57000054(L)0x

S3C2440A RISC MICROPROCESSOR REAL TIME CLOCK17-7ALARM DATE DATA (ALMDATE) REGISTERRegister Address R/W De

REAL TIME CLOCK S3C2440A RISC MICROPROCESSOR17-8BCD SECOND (BCDSEC) REGISTERRegister Address R/W Description Reset ValueBCDSEC 0x57000070(L)0x5700007

S3C2440A RISC MICROPROCESSOR REAL TIME CLOCK17-9BCD DATE (BCDDATE) REGISTERRegister Address R/W Descripti

REAL TIME CLOCK S3C2440A RISC MICROPROCESSOR17-10BCD YEAR (BCDYEAR) REGISTERRegister Address R/W Description Reset ValueBCDYEAR 0x57000088(L)0x570000

S3C2440A RISC MICROPROCESSOR PRODUCT OVERVIEW1-17Table 1-2. S3C2440A 289-Pin FBGA Pin Assignments (Sheet 8 of 9) (Continued)PinNumberPinNameDefaultFu

S3C2440A RISC MICROPROCESSOR WATCHDOG TIMER18-118 WATCHDOG TIMEROVERVIEWThe S3C2440A watchdog timer is us

WATCHDOG TIMER S3C2440A RISC MICROPROCESSOR18-2WATCHDOG TIMER OPERATIONFigure 18-1 shows the functional block diagram of the watchdog timer. The watc

S3C2440A RISC MICROPROCESSOR WATCHDOG TIMER18-3WATCHDOG TIMER SPECIAL REGISTERSWATCHDOG TIMER CONTROL (WT

WATCHDOG TIMER S3C2440A RISC MICROPROCESSOR18-4WATCHDOG TIMER DATA (WTDAT) REGISTERThe WTDAT register is used to specify the time-out duration. The c

S3C2440A RISC MICROPROCESSOR MMC/SD/SDIO CONTROLLER19-119 MMC/SD/SDIO CONTROLLERFEATURES— SD Memory Card S

MMC/SD/SDIO CONTROLLER S3C2440A RISC MICROPROCESSOR19-2SD OPERATIONA serial clock line synchronizes shifting and sampling of the information on the f

S3C2440A RISC MICROPROCESSOR MMC/SD/SDIO CONTROLLER19-3SDIO OPERATIONThere are two functions of SDIO operation: SDIO Interrupt receiving and Read Wait

MMC/SD/SDIO CONTROLLER S3C2440A RISC MICROPROCESSOR19-4SDI SPECIAL REGISTERSSDI Control Register (SDICON)Register Address R/W Description Reset Value

S3C2440A RISC MICROPROCESSOR MMC/SD/SDIO CONTROLLER19-5SDI Command Argument Register (SDICmdArg)Register Address R/W Description Reset ValueSDICmdArg

MMC/SD/SDIO CONTROLLER S3C2440A RISC MICROPROCESSOR19-6SDI Command Status Register (SDICmdSta)Register Address R/W Description Reset ValueSDICmdSta 0

PRODUCT OVERVIEW S3C2440A RISC MICROPROCESSOR1-18 Table 1-2. S3C2440A 289-Pin FBGA Pin Assignments (Sheet 9 of 9) (Continued)PinNumberPinNameDefaultFu

S3C2440A RISC MICROPROCESSOR MMC/SD/SDIO CONTROLLER19-7

MMC/SD/SDIO CONTROLLER S3C2440A RISC MICROPROCESSOR19-8SDI Response Register 2 (SDIRSP2)Register Address R/W Description Reset ValueSDIRSP2 0x5A00001

S3C2440A RISC MICROPROCESSOR MMC/SD/SDIO CONTROLLER19-9SDI Data Control Register (SDIDatCon)Register Address R/W Description Reset ValueSDIDatCon 0x5A

MMC/SD/SDIO CONTROLLER S3C2440A RISC MICROPROCESSOR19-10

S3C2440A RISC MICROPROCESSOR MMC/SD/SDIO CONTROLLER19-11SDI Data Remain Counter Register (ADIDatCnt)Register Address R/W Description Reset ValueSDIDat

MMC/SD/SDIO CONTROLLER S3C2440A RISC MICROPROCESSOR19-12SDI Fifo Status Register (SDIFSTA)Register Address R/W Description Reset ValueSDIFSTA 0x5A000

S3C2440A RISC MICROPROCESSOR MMC/SD/SDIO CONTROLLER19-13SDI Interrupt Mask Register (SDIIntMsk)Register Address R/W Description Reset ValueSDIIntMsk 0

MMC/SD/SDIO CONTROLLER S3C2440A RISC MICROPROCESSOR19-14SDI Interrupt Mask Register (SDIIntMsk) (Continued)SDIIntMsk Bit Description Initial ValueBus

S3C2440A RISC MICROPROCESSOR IIC-BUS I

IIC-BUS INTERFACE S3C2440A RISC MICROPROCESSOR20-2PCLKAddress RegisterSDA4-bit PrescalerIIC-Bus Control LogicIICSTATIICCONComparatorShift RegisterShif

S3C2440A RISC MICROPROCESSOR PRODUCT OVERVIEW1-19The table below shows I/O types and descriptions.Input (I)/Output (O) Type Descriptionsd12i(vdd12i

S3C2440A RISC MICROPROCESSOR IIC-BUS I

IIC-BUS INTERFACE S3C2440A RISC MICROPROCESSOR20-4DATA TRANSFER FORMATEvery byte placed on the SDA line should be eight bits in length. The bytes can

S3C2440A RISC MICROPROCESSOR IIC-BUS I

IIC-BUS INTERFACE S3C2440A RISC MICROPROCESSOR20-6READ-WRITE OPERATIONIn Transmitter mode, when the data is transferred, the IIC-bus interface will wa

S3C2440A RISC MICROPROCESSOR IIC-BUS I

IIC-BUS INTERFACE S3C2440A RISC MICROPROCESSOR20-8Write slave address toIICDS.Write 0xB0 (M/RStart) to IICSTAT.The data of the IICDS (slaveaddress) is

S3C2440A RISC MICROPROCESSOR IIC-BUS I

IIC-BUS INTERFACE S3C2440A RISC MICROPROCESSOR20-10IIC detects start signal. and, IICDSreceives data.IIC compares IICADD and IICDS (thereceived slave

S3C2440A RISC MICROPROCESSOR IIC-BUS I

IIC-BUS INTERFACE S3C2440A RISC MICROPROCESSOR20-12MULTI-MASTER IIC-BUS CONTROL/STATUS (IICSTAT) REGISTERRegister Address R/W Description Reset ValueI

PRODUCT OVERVIEW S3C2440A RISC MICROPROCESSOR1-20 SIGNAL DESCRIPTIONSTable 1-3. S3C2440A Signal Descriptions (Sheet 1 of 6)Signal Input/Output Descrip

S3C2440A RISC MICROPROCESSOR IIC-BUS I

IIC-BUS INTERFACE S3C2440A RISC MICROPROCESSOR20-14MULTI-MASTER IIC-BUS LINE CONTROL(IICLC) REGISTERRegister Address R/W Description Reset ValueIICLC

S3C2440A RISC MICROPROCESSOR IIS-BUS INTERFACE 21-121 IIS-BUS INTERFACEOVERVIEWCurrently, many digital aud

IIS-BUS INTERFACE S3C2440A RISC MICROPROCESSOR21-2BLOCK DIAGRAMADDRDATACNTLPCLKBRFCIPSR_AIPSR_BTxFIFORxFIFOSCLKGCHNCSFTRLRCKSCLKSDCDCLKMPLLinFigure 2

S3C2440A RISC MICROPROCESSOR IIS-BUS INTERFACE21-3DMA TRANSFERIn this mode, transmit or receive FIFO is acc

IIS-BUS INTERFACE S3C2440A RISC MICROPROCESSOR21-4IIS-bus Format (N=8 or 16)MSB(1st)2ndBitN-1thBitLSB(last)MSB(1st)2ndBitN-1thBitLSB(last)MSB(1st)LRC

S3C2440A RISC MICROPROCESSOR IIS-BUS INTERFACE21-5IIS-BUS INTERFACE SPECIAL REGISTERSIIS CONTROL (IISCON) R

IIS-BUS INTERFACE S3C2440A RISC MICROPROCESSOR21-6IIS MODE REGISTER (IISMOD) REGISTERRegister Address R/W Description Reset ValueIISMOD 0x55000004 (L

S3C2440A RISC MICROPROCESSOR IIS-BUS INTERFACE21-7IIS PRESCALER (IISPSR) REGISTERRegister Address R/W Descr

IIS-BUS INTERFACE S3C2440A RISC MICROPROCESSOR21-8IIS FIFO CONTROL (IISFCON) REGISTERRegister Address R/W Description Reset ValueIISFCON 0x5500000C (

S3C2440A MICROCONTROLLER vTable of Contents (Continued)Chapter 3 ARM Instruction Set (Continued)Single Data Transfer (LDR, STR)...

S3C2440A RISC MICROPROCESSOR PRODUCT OVERVIEW1-21Table 1-3. S3C2440A Signal Descriptions (Sheet 2 of 6) (Continued)Signal Input/OutputDescriptionsLCD

S3C2440A RISC MICROPROCESSOR SPI22-122 SPIOVERVIEWThe S3C2440A Serial Peripheral Interface (SPI) can interface with the serial data transfer. Th

SPI S3C2440A RISC MICROPROCESSOR22-2BLOCK DIAGRAM8bit Prescaler 1PCLKStatus Register 1Prescaler Register 1/SSnSS 0SCKSPICLK 0MOSISPIMOSI 0MISOSPIMISO

S3C2440A RISC MICROPROCESSOR SPI22-3SPI OPERATIONUsing the SPI interface, S3C2440A can send/receive 8-bit data simultaneously with an external device.

SPI S3C2440A RISC MICROPROCESSOR22-4SPI TRANSFER FORMATThe S3C2440A supports 4 different formats to transfer data. Figure 22-2 shows the four waveform

S3C2440A RISC MICROPROCESSOR SPI22-5TRANSMITTING PROCEDURE FOR DMA1. SPI is configured as DMA mode.2. DMA is configured properly.3. SPI requests DMA s

SPI S3C2440A RISC MICROPROCESSOR22-6SPI SPECIAL REGISTERSSPI CONTROL REGISTERRegister Address R/W Description Reset ValueSPCON0 0x59000000 R/W SPI cha

S3C2440A RISC MICROPROCESSOR SPI22-7SPI STATUS REGISTERRegister Address R/W Description Reset ValueSPSTA0 0x59000004 R SPI channel 0 status register 0

SPI S3C2440A RISC MICROPROCESSOR22-8SPI PIN CONTROL REGISTERWhen the SPI system is enabled, the direction of pins except nSS pin is controlled by MSTR

S3C2440A RISC MICROPROCESSOR SPI22-9SPI BAUD RATE PRESCALER REGISTERRegister Address R/W Description Reset ValueSPPRE0 0x5900000C R/W SPI cannel 0 bau

SPI S3C2440A RISC MICROPROCESSOR22-10NOTES

PRODUCT OVERVIEW S3C2440A RISC MICROPROCESSOR1-22 Table 1-3. S3C2440A Signal Descriptions (Sheet 3 of 6) (Continued)Signal Input/Output DescriptionsUA

S3C2440A RISC MICROPROCESSOR CAMERA INTERFACE23-123 CAMERA INTERFACEOVERVIEWThis chapter will explain the specification and defines the camera interfa

S3C2440A RISC MICROPROCESSOR CAMERA INTERFACE23-2

S3C2440A RISC MICROPROCESSOR CAMERA INTERFACE23-3TIMING DIAGRAMCAMVSYNCY Cb Y Cr Y Cb Y Cb Y CrCAMHREFCAMHREF(1H)CAMPCLKCAMDATA[7:0]VerticallinesHoriz

S3C2440A RISC MICROPROCESSOR CAMERA INTERFACE23-4

S3C2440A RISC MICROPROCESSOR CAMERA INTERFACE23-5CAMERA INTERFACE OPERATIONTWO DMA PATHSCAMIF has 2 DMA paths. P-path (Preview path) and C-path (Codec

S3C2440A RISC MICROPROCESSOR CAMERA INTERFACE23-6

S3C2440A RISC MICROPROCESSOR CAMERA INTERFACE23-7C-port Y 1C-port Cb 1C-port Cr 1C-port Y 2C-port Cb 2C-port Cr 2C-port Y 3C-port Cb 3C-port Cr 3C-por

S3C2440A RISC MICROPROCESSOR CAMERA INTERFACE23-8

S3C2440A RISC MICROPROCESSOR CAMERA INTERFACE23-9TIMING DIAGRAM FOR REGISTER SETTINGThe first register setting for frame capture command can occur any

S3C2440A RISC MICROPROCESSOR CAMERA INTERFACE23-10

S3C2440A RISC MICROPROCESSOR PRODUCT OVERVIEW1-23Table 1-3. S3C2440A Signal Descriptions (Sheet 4 of 6) (Continued)Signal Input/Output DescriptionSPI

S3C2440A RISC MICROPROCESSOR CAMERA INTERFACE23-11CAMERA INTERFACE SPECIAL REGISTERSSOURCE FORMAT REGISTERRegister Address R/W Description Reset Value

S3C2440A RISC MICROPROCESSOR CAMERA INTERFACE23-12

S3C2440A RISC MICROPROCESSOR CAMERA INTERFACE23-13GLOBAL CONTROL REGISTERRegister Address R/W Description Reset ValueCIGCTRL 0x4F000008 RW Global cont

S3C2440A RISC MICROPROCESSOR CAMERA INTERFACE23-14

S3C2440A RISC MICROPROCESSOR CAMERA INTERFACE23-15CB3 START ADDRESS REGISTERRegister Address R/W Description Reset ValueCICOCBSA3 0x4F000030 RWCb 3nd

S3C2440A RISC MICROPROCESSOR CAMERA INTERFACE23-16

S3C2440A RISC MICROPROCESSOR CAMERA INTERFACE23-17CODEC TARGET FORMAT REGISTERRegister Address R/W Description Reset ValueCICOTRGFMT 0x4F000048 RW Tar

S3C2440A RISC MICROPROCESSOR CAMERA INTERFACE23-18

S3C2440A RISC MICROPROCESSOR CAMERA INTERFACE23-19CODEC DMA CONTROL REGISTERRegister Address R/W Description Reset ValueCICOCTRL 0x4F00004C RW Codec D

S3C2440A RISC MICROPROCESSOR CAMERA INTERFACE23-20

PRODUCT OVERVIEW S3C2440A RISC MICROPROCESSOR1-24 Table 1-3. S3C2440A Signal Descriptions (Sheet 5 of 6) (Continued)Signal Input/Output DescriptionRes

S3C2440A RISC MICROPROCESSOR CAMERA INTERFACE23-21If ( SRC_Height >= 64 × DST_Height ) { Exit(-1); /* Out Of Vertical Scale Range */ }else if (S

S3C2440A RISC MICROPROCESSOR CAMERA INTERFACE23-22

S3C2440A RISC MICROPROCESSOR CAMERA INTERFACE23-23CODEC STATUS REGISTERRegister Address R/W Description Reset ValueCICOSTATUS 0x4F000064 R Codec path

S3C2440A RISC MICROPROCESSOR CAMERA INTERFACE23-24

S3C2440A RISC MICROPROCESSOR CAMERA INTERFACE23-25PREVIEW DMA CONTROL REGISTERRegister Address R/W Description Reset ValueCIPRCTRL 0x4F000080 RW Previ

S3C2440A RISC MICROPROCESSOR CAMERA INTERFACE23-26

S3C2440A RISC MICROPROCESSOR CAMERA INTERFACE23-27PREVIEW STATUS REGISTERRegister Address R/W Description Reset ValueCIPRSTATUS 0x4F000098 R Preview p

S3C2440A RISC MICROPROCESSOR CAMERA INTERFACE23-28

S3C2440A RISC MICROPROCESSOR AC97 CONT

AC97 CONTROLLER S3C2440A RISC MICROPROCESSOR24-2AC97 CONTROLLER OPERATIONBLOCK DIAGRAMFigure 24-1 shows the functional block diagram of the S3C2440A A

S3C2440A RISC MICROPROCESSOR PRODUCT OVERVIEW1-25Table 1-3. S3C2440A Signal Descriptions (Sheet 6 of 6) (Continued)Signal Input/Output DescriptionPow

S3C2440A RISC MICROPROCESSOR AC97 CONT

AC97 CONTROLLER S3C2440A RISC MICROPROCESSOR24-4OPERATION FLOW CHARTSystem reset or Cold resetSet GPIO and ReleaseINTMSK/SUBINTMSK bitsEnable Codec Re

S3C2440A RISC MICROPROCESSOR AC97 CONT

AC97 CONTROLLER S3C2440A RISC MICROPROCESSOR24-6AC-LINK OUTPUT FRAME (SDATA_OUT)SDATA_OUTBIT_CLKSYNCAC '97 samples SYNC assertion hereAC '97

S3C2440A RISC MICROPROCESSOR AC97 CONT

AC97 CONTROLLER S3C2440A RISC MICROPROCESSOR24-8Waking up the AC-link - Wake Up Triggered by the AC97 ControllerAC-link protocol is provided for a col

S3C2440A RISC MICROPROCESSOR AC97 CONT

AC97 CONTROLLER S3C2440A RISC MICROPROCESSOR24-10AC97 GLOBAL STATUS REGISTER (AC_GLBSTAT)Register Address R/W Description Reset ValueAC_GLBSTAT 0x5B00

S3C2440A RISC MICROPROCESSOR AC97 CONT

AC97 CONTROLLER S3C2440A RISC MICROPROCESSOR24-12AC97 MIC IN CHANNEL FIFO ADDRESS REGISTER (AC_MICADDR)Register Address R/W Description Reset ValueAC_

PRODUCT OVERVIEW S3C2440A RISC MICROPROCESSOR1-26 S3C2440A SPECIAL REGISTERSTable 1-4. S3C2440A Special Registers (Sheet 1 of 14)RegisterNameAddress(B

S3C2440A RISC MICROPROCESSOR BUS PRIORITIES25-125 BUS PRIORITIESOVERVIEWThe bus arbitration logic determin

BUS PRIORITIES S3C2440A RISC MICROPROCESSOR25-2NOTES

S3C2440A RISC MICROPROCESSOR MECHANICAL DATA26-126 MECHANICAL DATAPACKAGE DIMENSIONS14.0014.000.35 + 0.051.22289-FBG

MECHANICAL DATA S3C2440A RISC MICROPROCESSOR26-2A1 INDEX MARK0.80 x 16 = 12.80 ± 0.0514.000.800.80ABCDEFGHJKLMNPRTU891011121314151617 567 123414.000

S3C2440A RISC MICROPROCESSOR ELECTRICAL DATA 27-127 ELECTRICAL DATAABSOLUTE MAXIMUM RATINGSTable 27-1. Absolute Maximum RatingParameter Symbol Ratin

ELECTRICAL DATA S3C2440A RISC MICROPROCESSOR27-2RECOMMENDED OPERATING CONDITIONSTable 27-2. Recommended Operating ConditionsParameter Symbol Rating Un

S3C2440A RISC MICROPROCESSOR ELECTRICAL DATA 27-3D.C. ELECTRICAL CHARACTERISTICSTable 27-3 and 27-4 defines the DC electrical characteristics for th

ELECTRICAL DATA S3C2440A RISC MICROPROCESSOR27-4Normal I/O PAD DC Electrical Characteristics for Memory (VDDMOP=3.0V±0.3V, 3.3V±0.3V, TA= –40 to 85 °C

S3C2440A RISC MICROPROCESSOR ELECTRICAL DATA 27-5Normal I/O PAD DC Electrical Characteristics for I/O (VDDOP = 3.3V ± 0.3V, TA = –40 to 85 °C)Symbol

ELECTRICAL DATA S3C2440A RISC MICROPROCESSOR27-6Table 27-4. USB DC Electrical CharacteristicsSymbol Parameter Condition Min Max UnitVIHHigh level inpu

S3C2440A RISC MICROPROCESSOR PRODUCT OVERVIEW1-27Table 1-4. S3C2440A Special Registers (Sheet 2 of 14) (Continued)Register Name Address(B. Endian)Add

S3C2440A RISC MICROPROCESSOR ELECTRICAL DATA 27-7400Mhz Power consumption87mW88mW139mW68mW050100150200250Without DVS With DVSItem[mW]Core Power51% D

ELECTRICAL DATA S3C2440A RISC MICROPROCESSOR27-8A.C. ELECTRICAL CHARACTERISTICS1/2 VDD1/2 VDDtXTALCYCNOTE:Clock input is from the XTIpll pin.Figure 27

S3C2440A RISC MICROPROCESSOR ELECTRICAL DATA 27-9HCLK(internal)SCLKCLKOUT(HCLK)tHC2CKtHC2SCLKFigure 27-5. HCLK/CLKOUT/SCLK in case when EXTCLK is us

ELECTRICAL DATA S3C2440A RISC MICROPROCESSOR27-10nRESETXTIpll orEXTCLKVCOoutputMCU operates by XTIpll or EXTCLK clcok.ClockDisabletPLLFCLK is new freq

S3C2440A RISC MICROPROCESSOR ELECTRICAL DATA 27-11XTIpllVCOOutputClockDisableFCLKSeveral slow clocks (XTIpll or EXTCLK)Power_OFF mode is initiated.

ELECTRICAL DATA S3C2440A RISC MICROPROCESSOR27-12HCLKnGCSxtRADnOEDATAADDRnBExtRCDtRODtRODtRCDTacctRAD tRAD tRAD tRAD tRAD tRAD tRAD tRADtRDStRDHtRDStR

S3C2440A RISC MICROPROCESSOR ELECTRICAL DATA 27-13HCLKnGCSxtRADnOEDATAADDRnBExtRCDtRODtRODtRCDtRBEDtRBEDTacctRAD tRAD tRAD tRAD tRAD tRAD tRAD tRADt

ELECTRICAL DATA S3C2440A RISC MICROPROCESSOR27-14HCLKnGSnOEADDRtXnBRQSXnBREQtXnBRQHXnBACK'HZ''HZ''HZ'tXnBACKDtXnBACKDtHZ

S3C2440A RISC MICROPROCESSOR ELECTRICAL DATA 27-15HCLKnGCSxtRADTacsnOETcosDATAADDRnWBEx '1'TochTcahtRCDtRODtRDStRDHtRODtRCDtRADTaccFigure

ELECTRICAL DATA S3C2440A RISC MICROPROCESSOR27-16HCLKnGCSxtRADTacsnOETcosDATAADDRnBExTochTcahtRCDtRODtRDStRDHtRODtRCDtRADtRBEDtRBEDTaccFigure 27-13. R

PRODUCT OVERVIEW S3C2440A RISC MICROPROCESSOR1-28 Table 1-4. S3C2440A Special Registers (Sheet 3 of 14) (Continued)RegisterNameAddress(B. Endian)Addre

S3C2440A RISC MICROPROCESSOR ELECTRICAL DATA 27-17HCLKnGCSxtRADTacsnWETcosDATAADDRnWBExTochTcahtRCDtRWDtRDDtRWDtRCDtRADTcosTochtRWBEDtRWBEDTacctRDDF

ELECTRICAL DATA S3C2440A RISC MICROPROCESSOR27-18HCLKnGCSxtRADTacsnWETcosDATAADDRnBExTochTcahtRCDtRWDtRDDtRWDtRCDtRADtRBEDtRBEDTacctRDDFigure 27-15. R

S3C2440A RISC MICROPROCESSOR ELECTRICAL DATA 27-19HCLKnGCSxnOETacc = 6cyclenWaitDATAADDRTacsTacsdelayedtRCNOTE: The status of nWait is checked at (

ELECTRICAL DATA S3C2440A RISC MICROPROCESSOR27-20HCLKnGCSxtRADTacsnOETcosDATAADDRtRCDtRODtRDStRDHtRADTaccFigure 27-18. Masked-ROM Single READ Timing D

S3C2440A RISC MICROPROCESSOR ELECTRICAL DATA 27-21SCLKnSRAStSADTrpnSCASDATAADDR/BAnBExtSRDtSDStSDHSCKEA10/APnGCSxtSCSDnWEtSADtSCDtSWD'1'Tr

ELECTRICAL DATA S3C2440A RISC MICROPROCESSOR27-22SCLKnSRASnSCASADDR/BAnBExtXnBRQHtXnBRQSSCKEA10/APnGCSxnWE'1'XnBREQXnBACKEXTCLKtXnBACKDtXnBA

S3C2440A RISC MICROPROCESSOR ELECTRICAL DATA 27-23SCLKnSRAStSADnSCASDATAADDR/BAnBExtSRDSCKEA10/APnGCSxtSCSDnWEtSADtSCDtSWD'1'tSADtSCSDtSRD

ELECTRICAL DATA S3C2440A RISC MICROPROCESSOR27-24SCLKnSRAStSADTrpnSCASDATAADDR/BAnBExtSRDtSDStSDHSCKEA10/APnGCSxtSCSDnWEtSADtSCDtSWD'1'tSADt

S3C2440A RISC MICROPROCESSOR ELECTRICAL DATA 27-25SCLKnSRAStSADTrpnSCASDATAADDR/BAnBExtSRDtSDStSDHSCKEA10/APnGCSxtSCSDnWEtSADtSCDtSWD'1'tS

ELECTRICAL DATA S3C2440A RISC MICROPROCESSOR27-26SCLKnSRAStSADTrpnSCASDATAADDR/BAnBExtSRDSCKEA10/APnGCSxtSCSDnWEtSADtSCDtSWD'1'tSADtSCSDtSRD

S3C2440A RISC MICROPROCESSOR PRODUCT OVERVIEW1-29Table 1-4. S3C2440A Special Registers (Sheet 4 of 14) (Continued)RegisterNameAddress(B. Endian)Addre

S3C2440A RISC MICROPROCESSOR ELECTRICAL DATA 27-27SCLKnSRAStSADTrpnSCASDATAADDR/BAnBExtSRDtSDStSDHSCKEA10/APnGCSxtSCSDnWEtSADtSCDtSWD'1'Tr

ELECTRICAL DATA S3C2440A RISC MICROPROCESSOR27-28SCLKnSRAStSADTrpnSCASDATAADDR/BAnBExtSRDSCKEA10/APnGCSxtSCSDnWEtSADtSCDtSWDtSADtSCSDtSRD'1'

S3C2440A RISC MICROPROCESSOR ELECTRICAL DATA 27-29SCLKnSRAStSADTrpnSCASDATAADDR/BAnBExtSRDtSDDtSDDSCKEA10/APnGCSxtSCSDnWEtSADtSCDtSWD'1'tS

ELECTRICAL DATA S3C2440A RISC MICROPROCESSOR27-30SCLKnSRAStSADTrpnSCASDATAADDR/BAnBExtSRDtSDDtSDDSCKEA10/APnGCSxtSCSDnWEtSADtSCDtSWD'1'Trcdt

S3C2440A RISC MICROPROCESSOR ELECTRICAL DATA 27-31XSCLKtXRStXRStCADLtCADHtXADXnXDREQXnXDACKRead WriteMin. 3SCLKFigure 27-30. External DMA Timing Dia

ELECTRICAL DATA S3C2440A RISC MICROPROCESSOR27-32IISSCLKtLRCKIISLRCK (out)tSDOIISLRCK (out)tSDIHtSDISIISSDI (in)Figure 27-32. IIS Interface Timing Dia

S3C2440A RISC MICROPROCESSOR ELECTRICAL DATA 27-33SDCLKtSDCDSDCMD (out)tSDCHtSDCStSDDDSDCMD (in)tSDDHtSDDSSDDATA[3:0] (in)SDDATA[3:0] (out)Figure 27

ELECTRICAL DATA S3C2440A RISC MICROPROCESSOR27-34tACLStWRPH0tWRPH1CommandtWRPH0tWRPH1AddressHCLKALEnFWEDATA[7:0] DATA[7:0]HCLKCLEnFWEtCLEDtCLEDtWEDtWE

S3C2440A RISC MICROPROCESSOR ELECTRICAL DATA 27-35Table 27-7. Clock Timing Constants(VDDi, VDDalive, VDDiarm = 1.2 V ± 0.1 V, TA = –40 to 85 °C, VDD

ELECTRICAL DATA S3C2440A RISC MICROPROCESSOR27-36Table 27-8. ROM/SRAM Bus Timing Constants(VDDi, VDDalive, VDDiarm = 1.2 V ± 0.1 V, TA = –40 to 85 °C,

PRODUCT OVERVIEW S3C2440A RISC MICROPROCESSOR1-30 Table 1-4. S3C2440A Special Registers (Sheet 5 of 14) (Continued)RegisterNameAddress(B. Endian)Addre

S3C2440A RISC MICROPROCESSOR ELECTRICAL DATA 27-37Table 27-10. External Bus Request Timing Constants(VDD = 1.2 V ± 0.1 V, TA = –40 to 85 °C, VEXT =

ELECTRICAL DATA S3C2440A RISC MICROPROCESSOR27-38Table 27-12. TFT LCD Controller Module Signal Timing Constants(VDD = 1.2 V ± 0.05 V, TA = –40 to 85 °

S3C2440A RISC MICROPROCESSOR ELECTRICAL DATA 27-39Table 27-14. IIC BUS Controller Module Signal Timing(VDD = 1.2 V ± 0.05 V, TA = –40 to 85 °C, VEXT

ELECTRICAL DATA S3C2440A RISC MICROPROCESSOR27-40Table 27-16. SPI Interface Transmit/Receive Timing Constants(VDD = 1.2 V ± 0.1 V, TA = –40 to 85 °C,

S3C2440A RISC MICROPROCESSOR ELECTRICAL DATA 27-41Table 27-18. USB Full Speed Output Buffer Electrical Characteristics(VDD = 1.2 V ± 0.05 V, TA = –4

ELECTRICAL DATA S3C2440A RISC MICROPROCESSOR27-42Table 27-20. NAND Flash Interface Timing Constants(VDDi, VDDalive, VDDiarm = 1.2 V ± 0.1 V, TA = –40

This datasheet has been downloaded from:www.DatasheetCatalog.comDatasheets for electronic components.

vi S3C2440A MICROCONTROLLERTable of Contents (Continued)Chapter 3 ARM Instruction Set (Continued)Coprocessor Data Transfers (LDC, STC)...

S3C2440A RISC MICROPROCESSOR PRODUCT OVERVIEW1-31Table 1-4. S3C2440A Special Registers (Sheet 6 of 14) (Continued)RegisterNameAddress(B. Endian)Addre

PRODUCT OVERVIEW S3C2440A RISC MICROPROCESSOR1-32 Table 1-4. S3C2440A Special Registers (Sheet 7 of 14) (Continued)RegisterNameAddress(B. Endian)Addre

S3C2440A RISC MICROPROCESSOR PRODUCT OVERVIEW1-33Table 1-4. S3C2440A Special Registers (Sheet 8 of 14) (Continued)Register Name Address(B. Endian)Add

PRODUCT OVERVIEW S3C2440A RISC MICROPROCESSOR1-34 Table 1-4. S3C2440A Special Registers (Sheet 9 of 14) (Continued)Register Name Address(B. Endian)Add

S3C2440A RISC MICROPROCESSOR PRODUCT OVERVIEW1-35Table 1-4. S3C2440A Special Registers (Sheet 10 of 14) (Continued)Register Name Address(B. Endian)Ad

PRODUCT OVERVIEW S3C2440A RISC MICROPROCESSOR1-36 Table 1-4. S3C2440A Special Registers (Sheet 11 of 14) (Continued)RegisterNameAddress(B. Endian)Addr

S3C2440A RISC MICROPROCESSOR PRODUCT OVERVIEW1-37Table 1-4. S3C2440A Special Registers (Sheet 12 of 14) (Continued)RegisterNameAddress(B. Endian)Addr

PRODUCT OVERVIEW S3C2440A RISC MICROPROCESSOR1-38 Table 1-4. S3C2440A Special Registers (Sheet 13 of 14) (Continued)RegisterNameAddress(B. Endian)Addr

S3C2440A RISC MICROPROCESSOR PRODUCT OVERVIEW1-39Table 1-4. S3C2440A Special Registers (Sheet 14 of 14) (Continued)RegisterNameAddress(B. Endian)Addr

S3C2440A RISC MICROPROCESSOR PROGRAMMER'S MODEL 2-1 2 PROGRAMMER'S MODEL OVERVIEW S3C2440A is developed using the advanced ARM920T co

S3C2440A MICROCONTROLLER viiTable of Contents (Continued)Chapter 4 Thumb Instruction Set (Continued)Format 4: ALU Operations...

PROGRAMMER'S MODEL S3C2440A RISC MICROPROCESSOR 2-2 BIG-ENDIAN FORMAT In Big-Endian format, the most significant byte of a word is stored

S3C2440A RISC MICROPROCESSOR PROGRAMMER'S MODEL 2-3 OPERATING MODES ARM920T supports seven modes of operation: • User (usr): The normal ARM

PROGRAMMER'S MODEL S3C2440A RISC MICROPROCESSOR 2-4 r0r1r2r3r4r5r6r7r9r8r10r11r12r13r14r15 (PC)r0r1r2r3r4r5r6r7r9r8r10r11r12r13_svcr14_svc

S3C2440A RISC MICROPROCESSOR PROGRAMMER'S MODEL 2-5 The THUMB State Register Set The THUMB state register set is a subset of the ARM state s

PROGRAMMER'S MODEL S3C2440A RISC MICROPROCESSOR 2-6 The relationship between ARM and THUMB state registers The relationship between ARM a

S3C2440A RISC MICROPROCESSOR PROGRAMMER'S MODEL 2-7 Accessing Hi-Registers in THUMB State In THUMB state, registers R8-R15 ("Hi registe

PROGRAMMER'S MODEL S3C2440A RISC MICROPROCESSOR 2-8 The Condition Code Flags The N, Z, C and V bits are the condition code flags. These ma

S3C2440A RISC MICROPROCESSOR PROGRAMMER'S MODEL 2-9 Table 2-1. PSR Mode Bit Values M[4:0] Mode Visible THUMB state registers Visible ARM

PROGRAMMER'S MODEL S3C2440A RISC MICROPROCESSOR 2-10 EXCEPTIONS Exceptions arise whenever the normal flow of a program has to be halted te

S3C2440A RISC MICROPROCESSOR PROGRAMMER'S MODEL 2-11 Exception Entry/Exit Summary Table 2-2 summarizes the PC value preserved in the relevan

viii S3C2440A MICROCONTROLLERTable of Contents (Continued)Chapter 4 Thumb Instruction Set (Continued)Format 14: Push/Pop Registers...

PROGRAMMER'S MODEL S3C2440A RISC MICROPROCESSOR 2-12 IRQ The IRQ (Interrupt Request) exception is a normal interrupt caused by a LOW level

S3C2440A RISC MICROPROCESSOR PROGRAMMER'S MODEL 2-13 Software Interrupt The Software Interrupt Instruction (SWI) is used for entering Super

PROGRAMMER'S MODEL S3C2440A RISC MICROPROCESSOR 2-14 Exception Priorities When multiple exceptions arise at the same time, a fixed priorit

S3C2440A RISC MICROPROCESSOR PROGRAMMER'S MODEL 2-15 INTERRUPT LATENCIES The worst case latency for FIQ, assuming that it is enabled, consis

PROGRAMMER'S MODEL S3C2440A RISC MICROPROCESSOR 2-16 NOTES

S3C2440A RISC MICROPROCESSOR ARM INSTRUCTION SET3-13 ARM INSTRUCTION SETINSTRUCTION SET SUMMAYThis chapter describes the ARM instruction set in the AR

ARM INSTRUCTION SET S3C2440A RISC MICROPROCESSOR3-2NOTESSome instruction codes are not defined but does not cause Undefined instruction trap to be ta

S3C2440A RISC MICROPROCESSOR ARM INSTRUCTION SET3-3Table 3-1. The ARM Instruction Set (Continued)Mnemonic Instruction ActionMRC Move from coprocessor

ARM INSTRUCTION SET S3C2440A RISC MICROPROCESSOR3-4THE CONDITION FIELDIn ARM state, all instructions are conditionally executed according to the stat

S3C2440A RISC MICROPROCESSOR ARM INSTRUCTION SET3-5BRANCH AND EXCHANGE (BX)This instruction is only executed if the condition is true. The various con

S3C2440A MICROCONTROLLER ixTable of Contents (Continued)Chapter 5 Memory ControllerOverview...

ARM INSTRUCTION SET S3C2440A RISC MICROPROCESSOR3-6ExamplesADR R0, Into_THUMB + 1 Generate branch target address and set bit 0 high – hence it comes

S3C2440A RISC MICROPROCESSOR ARM INSTRUCTION SET3-7BRANCH AND BRANCH WITH LINK (B, BL)The instruction is only executed if the condition is true. The v

ARM INSTRUCTION SET S3C2440A RISC MICROPROCESSOR3-8ASSEMBLER SYNTAXItems in “{}” are optional. Items in “<>” must be present.B{L}{cond} <exp

S3C2440A RISC MICROPROCESSOR ARM INSTRUCTION SET3-9DATA PROCESSINGThe data processing instruction is only executed if the condition is true. The condi

ARM INSTRUCTION SET S3C2440A RISC MICROPROCESSOR3-10The instruction produces a result by performing a specified arithmetic or logical operation on on

S3C2440A RISC MICROPROCESSOR ARM INSTRUCTION SET3-11CPSR FLAGSThe data processing operations can be classified as logical or arithmetic. The logical o

ARM INSTRUCTION SET S3C2440A RISC MICROPROCESSOR3-12SHIFTSWhen the second operand is specified to be a shifted register, the operation of the barrel

S3C2440A RISC MICROPROCESSOR ARM INSTRUCTION SET3-1331Contents of RmValue of Operand 20carry out4500000Figure 3-7. Logical Shift RightThe form of the

ARM INSTRUCTION SET S3C2440A RISC MICROPROCESSOR3-14Rotate right (ROR) operations reuse the bits which "overshoot" in a logical shift right

S3C2440A RISC MICROPROCESSOR ARM INSTRUCTION SET3-15Register Specified Shift AmountOnly the least significant byte of the contents of Rs is used to de