ELECTRICAL DATA S3C2440A RISC MICROPROCESSOR
27-28
SCLK
nSRAS
t
SAD
Trp
nSCAS
DATA
ADDR/BA
nBEx
t
SRD
SCKE
A10/AP
nGCSx
t
SCSD
nWE
t
SAD
t
SCD
t
SWD
t
SAD
t
SCSD
t
SRD
'1'
'1'
'HZ'
Trc
t
CKED
'HZ'
'1'
'1'
'1'
'1'
'1'
t
CKED
NOTE:
Before executing an auto/self refresh command, all the banks must be in idle state.
Figure 27-27. SDRAM Self Refresh Timing Diagram (Trp=2, Trc=4)
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