Samsung YP-P10 User Manual download pdf (Page 254)

100

101

CLOCK & POWER MANAGEMENT S3C2440A RISC MICROPROCESSOR

7-20

CLOCK GENERATOR & POWER MANAGEMENT SPECIAL REGISTER

LOCK TIME COUNT REGISTER (LOCKTIME)

LOCKTIME 0x4C000000 R/W PLL lock time count register 0xFFFFFFFF

LOCKTIME Bit Description Initial State

U_LTIME [31:16] UPLL lock time count value for UCLK.

(U_LTIME > 300uS)

0xFFFF

M_LTIME [15:0] MPLL lock time count value for FCLK, HCLK, and PCLK

(M_LTIME > 300uS)

0xFFFF

MPLL Control Register

Mpll = (2 * m * Fin) / (p * 2

)

m = (MDIV + 8), p = (PDIV + 2), s = SDIV

UPLL Control Register

Upll = (m * Fin) / (p * 2

)

m = (MDIV + 8), p = (PDIV + 2), s = SDIV

PLL Value Selection Guide (MPLLCON)

1. F

OUT

= 2 * m * Fin / (p*2

), F

VCO

= 2 * m * Fin / p where: m=MDIV+8, p=PDIV+2, s=SDIV

2. 600MHz ≤ F

VCO

≤ 1.2GHz

3. 200MHz ≤ FCLK

OUT

≤ 600MHz

4. Don't set the P or M value as zero, that is, setting the P=000000, M=00000000 can cause malfunction of

the PLL.

5. The proper range of P and M: 1 ≤ P ≤ 62, 1 ≤ M ≤ 248

NOTE

Although there is the rule for choosing PLL value, we recommend only the values in the PLL value

recommendation

table. If you have to use another value, please contact us.

1 2 ... 249 250 251 252 253 254 255 256 257 258 259 ... 595 596

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Samsung YP-P10 User Manual Page 254

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