Samsung YP-P10 User Manual Page 367
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USB DEVICE S3C2440A RISC MICROPROCESSOR
13-12
END POINT0 CONTROL STATUS REGISTER (EP0_CSR)
This register has the control and status bits for Endpoint 0. Since a control transaction is involved with both IN and
OUT tokens, there is only one CSR register, mapped to the IN CSR1 register. (Share IN1_CSR and can access by
writing index register “0” and read/write IN1_CSR)
Register Address R/W Description Reset Value
EP0_CSR 0x52000184(L)
0x52000187(B)
R/W
(byte)
Endpoint 0 status register 0x00
EP0_CSR Bit MCU USB Description Initial State
SERVICED_SET
UP_END
[7] W CLEAR The MCU should write a "1" to this bit to clear
SETUP_END.
0
SERVICED_OUT
_PKT_RDY
[6] W CLEAR The MCU should write a "1" to this bit to clear
OUT_PKT_RDY.
0
SEND_STALL [5] R/W CLEAR MCU should write a "1" to this bit at the same
time it clears OUT_PKT_RDY, if it decodes an
invalid token.
0 = Finish the STALL condition
1 = The USB issues a STALL and shake to the
current control transfer.
0
SETUP_END [4] R SET Set by the USB when a control transfer ends
before DATA_END is set.
When the USB sets this bit, an interrupt is
generated to the MCU.
When such a condition occurs, the USB
flushes the FIFO and invalidates MCU access
to the FIFO.
0
DATA_END [3] SET CLEAR Set by the MCU on the conditions below:
1. After loading the last packet of data into the
FIFO, at the same time IN_PKT_RDY is set.
2. While it clears OUT_PKT_RDY after
unloading the last packet of data.
3. For a zero length data phase.
0
SENT_STALL [2] CLEAR SET Set by the USB if a control transaction is
stopped due to a protocol violation. An interrupt
is generated when this bit is set. The MCU
should write "0" to clear this bit.
0
IN_PKT_RDY [1] SET CLEAR Set by the MCU after writing a packet of data
into EP0 FIFO. The USB clears this bit once
the packet has been successfully sent to the
host. An interrupt is generated when the USB
clears this bit, so as the MCU to load the next
packet. For a zero length data phase, the MCU
sets DATA_END at the same time.
0
OUT_PKT_RDY [0] R SET Set by the USB once a valid token is written to
the FIFO. An interrupt is generated when the
USB sets this bit. The MCU clears this bit by
writing a "1" to the SERVICED_OUT_PKT_RDY
bit.
0
- S3C2440A 1
- Important Notice 2
- Table of Contents 3
- Table of Contents (Continued) 10
- List of Figures 22
- List of Figures (Continued) 23
- List of Tables 28
- List of Tables (Continued) 29
- 1 PRODUCT OVERVIEW 30
- FEATURES 31
- FEATURES (Continued) 32
- PIN ASSIGNMENTS 35
- @nRESET4 OSCin 47
- ← W Control and status group 56
- ← W R/W DMA 0 initial source 57
- ← W R/W DMA 3 initial source 57
- ← W RW Input source format 60
- ← W R/W Timer configuration 62
- ← W R/W Watchdog timer mode 64
- ← W R/W IIC control 64
- ← W R/W Port A control 65
- ← W R/W Reserved 66
- 2 PROGRAMMER'S MODEL 69
- THUMB State 74
- ARM State 74
- Lo-RegistersHi-Registers 74
- 3 ARM INSTRUCTION SET 85
- THE CONDITION FIELD 88
- BRANCH AND EXCHANGE (BX) 89
- [24] Link bit 91
- Examples 92
- DATA PROCESSING 93
- [6:5] Shift type 96
- [11:7] Shift amount 96
- [11:8] Shift register 96
- PSR TRANSFER (MRS, MSR) 102
- [19:16] Destination Register 106
- [20] Set Condition Code 106
- [21] Accumulate 106
- [31:28] Condition Field 106
- Big-Endian Configuration 114
- 1 = Up: add offset to base 118
- [6][5] S H 118
- SINGLE DATA SWAP (SWP) 131
- SOFTWARE INTERRUPT (SWI) 133
- 31 2427 19 15 135
- Cond CRm 135
- 28 16 111223 20 135
- 0CpCp#CRdCRn1110 CP Opc 135
- 8 7 5 4 3 0 135
- [11:8] Coprocessor Number 137
- EXAMPLES 139
- 4 THUMB INSTRUCTION SET 149
- FORMAT SUMMARY 150
- [2:0] Destination Register 153
- [5:3] Source Register 153
- [10:6] Immediate Vale 153
- [12:11] Opcode 153
- [8:6] Register/Immediate Vale 155
- [9] Opcode 155
- [10] Immediate Flag 155
- [7:0] Immediate Vale 157
- FORMAT 4: ALU OPERATIONS 159
- [6] Hi Operand Flag 2 161
- [7] Hi Operand Flag 1 161
- [9:8] Opcode 161
- FORMAT 6: PC-RELATIVE LOAD 164
- [5:3] Base Register 166
- [8:6] Offset Register 166
- [10] Byte/Word Flag 166
- [11] Load/Store Flag 166
- [10] Sign-Extended Flag 168
- [11] H Flag 168
- [10:6] Offset Register 170
- [12] Byte/Word Flad 170
- INSTRUCTION CYCLE TIMES 171
- [10:6] Immediate Value 172
- [7:0] Immediate Value 174
- [10:8] Destination Register 174
- [11] Load/Store Bit 174
- [7:0] 8-bit Unsigned Constant 176
- [11] Source 176
- [6:0] 7-bit Immediate Value 178
- [7] Sign Flag 178
- FORMAT 14: PUSH/POP REGISTERS 179
- [7:0] Register List 181
- [10:8] Base Register 181
- [7:0] 8-bit Signed Immediate 182
- [11:8] Condition 182
- [7:0] Comment Field 184
- [10:0] Immediate Value 185
- [11] Low/High Offset Bit 186
- LR := temp 187
- INSTRUCTION SET EXAMPLES 188
- 5 MEMORY CONTROLLER 193
- Table 5-1. Bank 6/7 Addresses 195
- FUNCTION DESCRIPTION 196
- ROM Memory Interface Examples 200
- PROGRAMMABLE ACCESS CYCLE 204
- 6 NAND FLASH CONTORLLER 213
- NAND FLASH MEMORY TIMING 216
- SOFTWARE MODE 217
- ECC (ERROR CORRECTION CODE) 219
- NAND FLASH MEMORY MAPPING 221
- CLOCK & POWER MANAGEMENT 235
- FUNCTIONAL DESCRIPTION 236
- HDIVN PDIVN 237
- Management 244
- S3C2440A 251
- approximately 7 NOP) 255
- OVERVIEW 260
- DMA REQUEST SOURCES 261
- DMA OPERATION 261
- Read Write 262
- Demand Mode 263
- Handshake Mode 263
- Double Synch 264
- DMA SPECIAL REGISTERS 266
- 9 I/O PORTS 274
- PORT CONTROL DESCRIPTIONS 280
- I/O PORT CONTROL REGISTER 281
- DCLKnDIV + 1 299
- DCLKnCMP + 1 299
- 10 PWM TIMER 312
- PWM TIMER OPERATION 314
- 50 110 4040 6020 317
- 3 7 9 10 317
- Inverter off 319
- Inverter on 319
- PWM TIMER CONTROL REGISTERS 322
- BLOCK DIAGRAM 333
- UART SPECIAL REGISTERS 341
- Delta CTS 350
- Read_UMSTAT 350
- 12 USB HOST CONTROLLER 354
- 13 USB DEVICE CONTROLLER 356
- Non Indexed Registers 358
- 14 INTERRUPT CONTROLLER 378
- 15 LCD CONTROLLER 396
- STN LCD CONTROLLER OPERATION 399
- , B = 2 399
- LCD Panel 404
- Full Frame Timing(MMODE = 0) 410
- TFT LCD CONTROLLER OPERATION 411
- P1 P2 P3 P4 P5 412
- P6 P7 P8 P10 P11 P12P9 414
- LEGEND: 424
- AIN5, AIN6, AIN7) for ADC 444
- 17 REAL TIME CLOCK 450
- 15~ 22pF 452
- 18 WATCHDOG TIMER 460
- 19 MMC/SD/SDIO CONTROLLER 464
- SD OPERATION 465
- SDIO OPERATION 466
- SDI SPECIAL REGISTERS 467
- 20 IIC-BUS INTERFACE 478
- Clock to Output 482
- 21 IIS-BUS INTERFACE 492
- FUNCTIONAL DESCRIPTIONS 493
- AUDIO SERIAL INTERFACE FORMAT 494
- 22 SPI 500
- SPI OPERATION 502
- SPI TRANSFER FORMAT 503
- SPI SPECIAL REGISTERS 505
- 23 CAMERA INTERFACE 510
- Figure 23-1. CAMIF Overview 511
- CAMERA INTERFACE OPERATION 514
- ITU-601/656 YCbCr 517
- 4:2:2 8-bit input timing 517
- Little endian method 517
- < Frame Capture Start > 518
- ImgCptEn(cmd) 519
- LastIRQEn 519
- FrameCnt 519
- 1 = Window offset enable 521
- 24 AC97 CONTROLLER 538
- AC97 CONTROLLER OPERATION 539
- INTERNAL DATA PATH 540
- OPERATION FLOW CHART 541
- SDATA_OUT 542
- SDATA_IN 542
- 0 1 2 3 4 5 6 7 8 9 10 11 12 542
- AC97 POWERDOWN 544
- 25 BUS PRIORITIES 550
- 26 MECHANICAL DATA 552
- 27 ELECTRICAL DATA 554
- Application 555
- (Unit: mA) 560
- (internal) 561
- 1. HSYNC period 591
- 2. VCLK period 591
- SDAH) is minimum 0ns 592
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