Samsung YP-P10 User Manual download pdf (Page 591)

100

101

ELECTRICAL DATA S3C2440A RISC MICROPROCESSOR

27-38

Table 27-12. TFT LCD Controller Module Signal Timing Constants

= 1.2 V ± 0.05 V, T

= –40 to 85 °C, V

EXT

= 3.3V ± 0.3V)

Parameter Symbol Min Typ Max Units

Vertical sync pulse width Tvspw VSPW + 1 – –

Phclk

(1)

Vertical back porch delay Tvbpd VBPD+1 – – Phclk

Vertical front porch delay Tvfpd VFPD+1 – – Phclk

VCLK pulse width Tvclk 1 – –

Pvclk

(2)

VCLK pulse width high Tvclkh 0.5 – – Pvclk

VCLK pulse width low Tvclkl 0.5 – – Pvclk

Hsync setup to VCLK falling edge Tl2csetup 0.5 – – Pvclk

VDEN setup to VCLK falling edge Tde2csetup 0.5 – – Pvclk

VDEN hold from VCLK falling edge Tde2chold 0.5 – – Pvclk

VD setup to VCLK falling edge Tvd2csetup 0.5 – – Pvclk

VD hold from VCLK falling edge Tvd2chold 0.5 – – Pvclk

VSYNC setup to HSYNC falling edge Tf2hsetup HSPW + 1 – – Pvclk

VSYNC hold from HSYNC falling edge Tf2hhold HBPD + HFPD +

HOZVAL + 3

– – Pvclk

NOTES:

1. HSYNC period

2. VCLK period

Table 27-13. IIS Controller Module Signal Timing Constants

= 1.2 V ± 0.1 V, T

= –40 to 85 °C, V

EXT

= 3.3V ± 0.3V)

Parameter Symbol Min Typ. Max Unit

IISLRCK delay time t

LRCK

0 – 3 ns

IISDO delay time t

SDO

1 – 2 ns

IISDI input setup time t

SDIS

13 – – ns

IISDI input hold time t

SDIH

1 – – ns

CODEC clock frequency f

CODEC

1/16 – 1 f

IIS_BLOCK

1 2 ... 586 587 588 589 590 591 592 593 594 595 596

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