Samsung YP-P10 User Manual download pdf (Page 589)

ELECTRICAL DATA S3C2440A RISC MICROPROCESSOR

27-36

Table 27-8. ROM/SRAM Bus Timing Constants

(V

DDi,

V

DDalive,

V

DDiarm

= 1.2 V ± 0.1 V, T

A

= –40 to 85 °C, V

DDMOP

= 3.3V ± 0.3V / 3.0V ± 0.3V / 2.5V ± 0.2V / 1.8V

± 0.1V)

Parameter Symbol Min

(V

DDMOP

=

3.3V/3.0V/2.5V/1.8V)

Typ Max

(V

DDMOP

=

3.3V/3.0V/2.5V/1.8V)

Unit

ROM/SRAM address delay t

RAD

2 / 2 / 2 / 3 – 6 / 6 / 7 / 8 ns

ROM/SRAM chip select delay t

RCD

2 / 2 / 3 / 3 – 6 / 6 / 6 / 7 ns

ROM/SRAM output enable delay t

ROD

2 / 2 / 2 / 3 – 5 / 5 / 5 / 6 ns

ROM/SRAM read data setup time. t

RDS

1 / 1 / 1 / 2 – – / – / – / – ns

ROM/SRAM read data hold time. t

RDH

0 / 0 / 0 / 0 – – / – / – / – ns

ROM/SRAM byte enable delay t

RBED

2 / 2 / 2 / 3 – 5 / 5 / 5 / 7 ns

ROM/SRAM write byte enable delay t

RWBED

2 / 2 / 2 / 3 – 5 / 5 / 6 / 7 ns

ROM/SRAM output data delay t

RDD

2 / 2 / 2 / 2 – 6 / 6 / 6 / 7 ns

ROM/SRAM external wait setup time t

WS

3 / 3 / 4 / 4 – – / – / – / – ns

ROM/SRAM external wait hold time t

WH

0 / 0 / 0 / 0 – – / – / – / – ns

ROM/SRAM write enable delay t

RWD

2 / 2 / 2 / 3 – 5 / 5 / 6 / 7 ns

Table 27-9. Memory Interface Timing Constants

(V

DDi,

V

DDalive,

V

DDiarm

= 1.2 V ± 0.1 V, T

A

= –40 to 85 °C, V

DDMOP

= 3.3V ± 0.3V / 3.0V ± 0.3V / 2.5V ± 0.2V / 1.8V

± 0.1V)

Parameter Symbol Min Typ Max Unit

SDRAM address delay t

SAD

1 – 4 ns

SDRAM chip select delay t

SCSD

1 – 3 ns

SDRAM row active delay t

SRD

1 – 3 ns

SDRAM column active delay t

SCD

1 – 3 ns

SDRAM byte enable delay t

SBED

1 – 3 ns

SDRAM write enable delay t

SWD

1 – 2 ns

SDRAM read data setup time t

SDS

2 / 3 / 3 / 5 * – – ns

SDRAM read data hold time t

SDH

0 – – ns

SDRAM output data delay t

SDD

1 – 4 ns

SDRAM clock enable delay T

cked

2 – 3 ns

NOTE: Minimum t

SDS

= 2ns / 3ns / 3ns, when V

DDMOP

= 3.3V / 3.0V / 2.5V / 1.8V respectively.

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