Samsung YP-P10 User Manual download pdf (Page 26)

S3C2440A MICROCONTROLLER xxvii

List of Figures (Continued)

Figure Title Page

Number Number

21-1 IIS-Bus Block Diagram.....................................................................................................21-2

21-2 IIS-Bus and MSB (Left)-justified Data Interface Formats ......................................................21-4

22-1 SPI Block Diagram..........................................................................................................22-2

22-2 SPI Transfer Format.........................................................................................................22-4

23-1 CAMIF Overview..............................................................................................................23-2

23-2 ITU-R BT 601 Input Timing Diagram...................................................................................23-3

23-3 ITU-R BT 656 Input Timing Diagram...................................................................................23-3

23-4 Two DMA Paths ..............................................................................................................23-5

23-5 CAMIF Clock Generation..................................................................................................23-6

23-6 Ping-Pong Memory Hierarchy ...........................................................................................23-7

23-7 Memory Storing Style......................................................................................................23-8

23-8 Timing Diagram for Register Setting ..................................................................................23-9

23-9 Timing diagram for last IRQ ..............................................................................................23-10

23-10 Window Offset Scheme....................................................................................................23-12

23-11 Image Mirror and Rotation ................................................................................................23-18

23-12 Scaling Scheme..............................................................................................................23-20

24-1 AC97 Block Diagram .......................................................................................................24-2

24-2 Internal Data Path............................................................................................................24-3

24-3 AC97 Operation Flow Chart ..............................................................................................24-4

24-4 Bi-directional AC-link Frame with Slot Assignments............................................................24-5

24-5 AC-link Output Frame......................................................................................................24-6

24-6 AC-link Input Frame.........................................................................................................24-6

24-7 AC97 Powerdown Timing Diagram.....................................................................................24-7

24-8 AC97 Power down/Power up Flow.....................................................................................24-8

26-1 289-FBGA-1414 Package Dimension 1 (Top View) .............................................................26-1

26-2 289-FBGA-1414 Package Dimension 2 (Bottom View)........................................................26-2

27-1 Power Consumption Example Comparison when Applied DVS Scheme................................27-7

27-2 XTIpll Clock Timing Diagram .............................................................................................27-8

27-3 EXTCLK Clock Input Timing Diagram.................................................................................27-8

27-4 EXTCLK/HCLK in case when EXTCLK is used Without the PLL...........................................27-8

27-5 HCLK/CLKOUT/SCLK in case when EXTCLK is used .........................................................27-9

27-6 Manual Reset Input Timing Diagram..................................................................................27-9

27-7 Power-On Oscillation Setting Timing Diagram ....................................................................27-10

27-8 Sleep Mode Return Oscillation Setting Timing Diagram.......................................................27-11

27-9 ROM/SRAM Burst READ Timing Diagram (I)

(Tacs=0, Tcos=0, Tacc=2, Toch=0, Tcah=0, PMC=0, ST=0, DW=16bit)...............................27-12

27-10 ROM/SRAM Burst READ Timing Diagram (II)

(Tacs=0, Tcos=0, Tacc=2, Toch=0, Tcah=0, PMC=0, ST=1, DW=16bit)...............................27-13

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