Samsung YP-P10 User Manual download pdf (Page 368)

100

101

S3C2440A RISC MICROPROCESSOR USB DEVICE

13-13

END POINT IN CONTROL STATUS REGISTER (IN_CSR1_REG/IN_CSR2_REG)

IN_CSR1_REG 0x52000184(L)

0x52000187(B)

R/W

(byte)

IN END POINT control status register1 0x00

IN_CSR1_REG Bit MCU USB Description Initial State

Reserved [7] – – – –

CLR_DATA_

TOGGLE

[6] R/W R/

CLEAR

Used in set-up procedure.

0: There are alternation of DATA0 and DATA1

1: The data toggle bit is cleared and PID in

packet will maintain DATA0

SENT_STALL [5] R/

CLEAR

SET Set by the USB when an IN token issues a

STALL handshake, after the MCU sets

SEND_STALL bit to start STALL handshaking.

When the USB issues a STALL handshake,

IN_PKT_RDY is cleared

SEND_STALL [4] W/R R 0: The MCU clears this bit to finish the STALL

condition.

1: The MCU issues a STALL handshake to the

USB.

FIFO_FLUSH [3] R/W CLEAR Set by the MCU if it intends to flush the packet

in Input-related FIFO. This bit is cleared by the

USB when the FIFO is flushed. The MCU is

interrupted when this happens. If a token is in

process, the USB waits until the transmission

is complete before FIFO flushing. If two packets

are loaded into the FIFO, only first packet (The

packet is intended to be sent to the host) is

flushed, and the corresponding IN_PKT_RDY bit

is cleared

Reserved [2:1] – – – –

IN_PKT_RDY [0 R/SET CLEAR Set by the MCU after writing a packet of data

into the FIFO.

The USB clears this bit once the packet has

been successfully sent to the host.

An interrupt is generated when the USB clears

this bit, so the MCU can load the next packet.

While this bit is set, the MCU will not be able to

write to the FIFO.

If the MCU sets SEND STALL bit, this bit

cannot be set.

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Samsung YP-P10 User Manual Page 368

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