Samsung YP-P10 User Manual download pdf (Page 27)

xxviii S3C2440A MICROCONTROLLER

List of Figures (Continued)

Figure Title Page

Number Number

27-11 External Bus Request in ROM/SRAM Cycle

(Tacs=0, Tcos=0, Tacc=8, Toch=0, Tcah=0, PMC=0, ST=0)...............................................27-14

27-12 ROM/SRAM READ Timing Diagram (I)

(Tacs=2, Tcos=2, Tacc=4, Toch=2, Tcah=2, PMC=0, ST=0)...............................................27-15

27-13 ROM/SRAM READ Timing Diagram (II)

(Tacs=2, Tcos=2, Tacc=4, Toch=2, Tcah=2cycle, PMC=0, ST=1) .......................................27-16

27-14 ROM/SRAM WRITE Timing Diagram (I)

(Tacs=2,Tcos=2,Tacc=4,Toch=2, Tcah=2, PMC=0, ST=0...................................................27-17

27-15 ROM/SRAM WRITE Timing Diagram (II)

(Tacs=2, Tcos=2, Tacc=4, Toch=2, Tcah=2, PMC=0, ST=1)...............................................27-18

27-16 External nWAIT READ Timing Diagram

(Tacs=0, Tcos=0, Tacc=6, Toch=0, Tcah=0, PMC=0, ST=0)...............................................27-19

27-17 External nWAIT WRITE Timing Diagram

(Tacs=0, Tcos=0, Tacc=4, Toch=0, Tcah=0, PMC=0, ST=0)...............................................27-19

27-18 Masked-ROM Single READ Timing Diagram (Tacs=2, Tcos=2, Tacc=8, PMC=01/10/11).......27-20

27-19 Masked-ROM Consecutive READ Timing Diagram

(Tacs=0, Tcos=0, Tacc=3, Tpac=2, PMC=01/10/11)...........................................................27-20

27-20 SDRAM Single Burst READ Timing Diagram (Trp=2, Trcd=2, Tcl=2, DW=16bit)....................27-21

27-21 External Bus Request in SDRAM Timing Diagram (Trp=2, Trcd=2, Tcl=2).............................27-22

27-22 SDRAM MRS Timing Diagram..........................................................................................27-23

27-23 SDRAM Single READ Timing Diagram (I) (Trp=2, Trcd=2, Tcl=2) .........................................27-24

27-24 SDRAM Single READ Timing Diagram (II) (Trp=2, Trcd=2, Tcl=3).........................................27-25

27-25 SDRAM Auto Refresh Timing Diagram (Trp=2, Trc=4).........................................................27-26

27-26 SDRAM Page Hit-Miss READ Timing Diagram (Trp=2, Trcd=2, Tcl=2)..................................27-27

27-27 SDRAM Self Refresh Timing Diagram (Trp=2, Trc=4) ..........................................................27-28

27-28 SDRAM Single Write Timing Diagram (Trp=2, Trcd=2) ........................................................27-29

27-29 SDRAM Page Hit-Miss Write Timing Diagram (Trp=2, Trcd=2, Tcl=2)...................................27-30

27-30 External DMA Timing Diagram (Handshake, Single transfer)................................................27-31

27-31 TFT LCD Controller Timing Diagram...................................................................................27-31

27-32 IIS Interface Timing Diagram.............................................................................................27-32

27-33 IIC Interface Timing Diagram.............................................................................................27-32

27-34 SD/MMC Interface Timing Diagram....................................................................................27-33

27-35 SPI Interface Timing Diagram (CPHA=1, CPOL=1) .............................................................27-33

27-36 NAND Flash Address/Command Timing Diagram ...............................................................27-34

27-37 NAND Flash Timing Diagram............................................................................................27-34

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Samsung YP-P10 User Manual Page 27