Samsung YP-P10 User Manual download pdf (Page 333)

UART S3C2440A RISC MICROPROCESSOR

BLOCK DIAGRAM

Peripheral BUS

Clock Source

(PCLK, FCLK/n,UEXTCLK)

Transmit FIFO Register

Transmit Holding Register

(Non-FIFO mode)

Receive FIFO Register

Receive Holding Register

(Non-FIFO mode only)

In FIFO mode, all 64 Byte of Buffer register are used as FIFO register.

In non-FIFO mode, only 1 Byte of Buffer register is used as Holding register.

Transmit Shifter

Transmit Buffer

Receive Shifter

Receive Buffer

Figure 11-1. UART Block Diagram (with FIFO)

Samsung YP-P10 User Manual Page 333