S3C2440A RISC MICROPROCESSOR I/O PORTS
9-25
MISCELLANEOUS CONTROL REGISTER (MISCCR) (Continued)
MISCCR Bit Description Reset Value
CLKSEL1
(Note)
[10:8] Select source clock with CLKOUT1 pad
000 = MPLL output
001 = UPLL output
010 = RTC clock output
011 = HCLK
100 = PCLK
101 = DCLK1
11x = reserved
000
Reserved [7] – 0
CLKSEL0
(Note)
[6:4] Select source clock with CLKOUT0 pad
000 = MPLL INPUT Clock(XTAL)
001 = UPLL output
010 = FCLK
011 = HCLK
100 = PCLK
101 = DCLK0
11x = reserved
010
SEL_USBPAD [3] USB1 Host/Device select register.
0 = Use USB1 as device
1 = Use USB1 as host
0
Reserved [2] Reserved 0
SPUCR1 [1] 0 = DATA[31:16] port pull-up resister is enabled
1 = DATA[31:16] port pull-up resister is disabled
0
SPUCR0 [0] 0 = DATA[15:0] port pull-up resister is enabled
1 = DATA[15:0] port pull-up resister is disabled
0
NOTE: We recommend not to use this ouput pad to other device’s pll clock source.
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