Samsung YP-P10 User Manual Page 41
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PRODUCT OVERVIEW S3C2440A RISC MICROPROCESSOR
1-12
Table 1-2. S3C2440A 289-Pin FBGA Pin Assignments (Sheet 3 of 9) (Continued)
Pin
Number
Pin
Name
Default
Function
I/O State
@BUS REQ
I/O State
@Sleep
I/O State
@nRESET
I/O
Type
E13 DATA19 DATA19 Hi-z Hi-z,O(L) I b12s
E12 DATA20 DATA20 Hi-z Hi-z,O(L) I b12s
E16 DATA21 DATA21 Hi-z Hi-z,O(L) I b12s
F15 DATA22 DATA22 Hi-z Hi-z,O(L) I b12s
G13 DATA23 DATA23 Hi-z Hi-z,O(L) I b12s
E17 DATA24 DATA24 Hi-z Hi-z,O(L) I b12s
G12 DATA25 DATA25 Hi-z Hi-z,O(L) I b12s
F14 DATA26 DATA26 Hi-z Hi-z,O(L) I b12s
F12 DATA27 DATA27 Hi-z Hi-z,O(L) I b12s
G11 DATA28 DATA28 Hi-z Hi-z,O(L) I b12s
G16 DATA29 DATA29 Hi-z Hi-z,O(L) I b12s
H13 DATA30 DATA30 Hi-z Hi-z,O(L) I b12s
F13 DATA31 DATA31 Hi-z Hi-z,O(L) I b12s
P12 DN0 DN0 – – AI us
N11 DP0 DP0 – – AI us
N12 DN1/PDN0 DN1 –/– – AI us
U14 DP1/PDP0 DP1 –/– – AI us
N17 EINT0/GPF0 GPF0 –/– Hi-z/– I t8
M16 EINT1/GPF1 GPF1 –/– Hi-z/– I t8
L13 EINT2/GPF2 GPF2 –/– Hi-z/– I t8
M15 EINT3/GPF3 GPF3 –/– Hi-z/– I t8
M17 EINT4/GPF4 GPF4 –/– Hi-z/– I t8
L14 EINT5/GPF5 GPF5 –/– Hi-z/– I t8
L15 EINT6/GPF6 GPF6 –/– Hi-z/– I t8
L16 EINT7/GPF7 GPF7 –/– Hi-z/– I t8
N9 EINT8/GPG0 GPG0 –/– Hi-z/– I t8
T9 EINT9/GPG1 GPG1 –/– Hi-z/– I t8
J10 EINT10/nSS0/GPG2 GPG2 –/–/– Hi-z/Hi-z/– I t8
R10 EINT11/nSS1/GPG3 GPG3 –/–/– Hi-z/Hi-z/– I t8
P11 EINT12/LCD_PWREN/GPG
4
GPG4 –/–/– Hi-z/O(L)/– I t8
K10 EINT13/SPIMISO1/GPG5 GPG5 –/–/– Hi-z/Hi-z/– I t8
R11 EINT14/SPIMOSI1/GPG6 GPG6 –/–/– Hi-z/Hi-z/– I t8
L10 EINT15/SPICLK1/GPG7 GPG7 –/–/– Hi-z/Hi-z/– I t8
- S3C2440A 1
- Important Notice 2
- Table of Contents 3
- Table of Contents (Continued) 10
- List of Figures 22
- List of Figures (Continued) 23
- List of Tables 28
- List of Tables (Continued) 29
- 1 PRODUCT OVERVIEW 30
- FEATURES 31
- FEATURES (Continued) 32
- PIN ASSIGNMENTS 35
- @nRESET4 OSCin 47
- ← W Control and status group 56
- ← W R/W DMA 0 initial source 57
- ← W R/W DMA 3 initial source 57
- ← W RW Input source format 60
- ← W R/W Timer configuration 62
- ← W R/W Watchdog timer mode 64
- ← W R/W IIC control 64
- ← W R/W Port A control 65
- ← W R/W Reserved 66
- 2 PROGRAMMER'S MODEL 69
- THUMB State 74
- ARM State 74
- Lo-RegistersHi-Registers 74
- 3 ARM INSTRUCTION SET 85
- THE CONDITION FIELD 88
- BRANCH AND EXCHANGE (BX) 89
- [24] Link bit 91
- Examples 92
- DATA PROCESSING 93
- [6:5] Shift type 96
- [11:7] Shift amount 96
- [11:8] Shift register 96
- PSR TRANSFER (MRS, MSR) 102
- [19:16] Destination Register 106
- [20] Set Condition Code 106
- [21] Accumulate 106
- [31:28] Condition Field 106
- Big-Endian Configuration 114
- 1 = Up: add offset to base 118
- [6][5] S H 118
- SINGLE DATA SWAP (SWP) 131
- SOFTWARE INTERRUPT (SWI) 133
- 31 2427 19 15 135
- Cond CRm 135
- 28 16 111223 20 135
- 0CpCp#CRdCRn1110 CP Opc 135
- 8 7 5 4 3 0 135
- [11:8] Coprocessor Number 137
- EXAMPLES 139
- 4 THUMB INSTRUCTION SET 149
- FORMAT SUMMARY 150
- [2:0] Destination Register 153
- [5:3] Source Register 153
- [10:6] Immediate Vale 153
- [12:11] Opcode 153
- [8:6] Register/Immediate Vale 155
- [9] Opcode 155
- [10] Immediate Flag 155
- [7:0] Immediate Vale 157
- FORMAT 4: ALU OPERATIONS 159
- [6] Hi Operand Flag 2 161
- [7] Hi Operand Flag 1 161
- [9:8] Opcode 161
- FORMAT 6: PC-RELATIVE LOAD 164
- [5:3] Base Register 166
- [8:6] Offset Register 166
- [10] Byte/Word Flag 166
- [11] Load/Store Flag 166
- [10] Sign-Extended Flag 168
- [11] H Flag 168
- [10:6] Offset Register 170
- [12] Byte/Word Flad 170
- INSTRUCTION CYCLE TIMES 171
- [10:6] Immediate Value 172
- [7:0] Immediate Value 174
- [10:8] Destination Register 174
- [11] Load/Store Bit 174
- [7:0] 8-bit Unsigned Constant 176
- [11] Source 176
- [6:0] 7-bit Immediate Value 178
- [7] Sign Flag 178
- FORMAT 14: PUSH/POP REGISTERS 179
- [7:0] Register List 181
- [10:8] Base Register 181
- [7:0] 8-bit Signed Immediate 182
- [11:8] Condition 182
- [7:0] Comment Field 184
- [10:0] Immediate Value 185
- [11] Low/High Offset Bit 186
- LR := temp 187
- INSTRUCTION SET EXAMPLES 188
- 5 MEMORY CONTROLLER 193
- Table 5-1. Bank 6/7 Addresses 195
- FUNCTION DESCRIPTION 196
- ROM Memory Interface Examples 200
- PROGRAMMABLE ACCESS CYCLE 204
- 6 NAND FLASH CONTORLLER 213
- NAND FLASH MEMORY TIMING 216
- SOFTWARE MODE 217
- ECC (ERROR CORRECTION CODE) 219
- NAND FLASH MEMORY MAPPING 221
- CLOCK & POWER MANAGEMENT 235
- FUNCTIONAL DESCRIPTION 236
- HDIVN PDIVN 237
- Management 244
- S3C2440A 251
- approximately 7 NOP) 255
- OVERVIEW 260
- DMA REQUEST SOURCES 261
- DMA OPERATION 261
- Read Write 262
- Demand Mode 263
- Handshake Mode 263
- Double Synch 264
- DMA SPECIAL REGISTERS 266
- 9 I/O PORTS 274
- PORT CONTROL DESCRIPTIONS 280
- I/O PORT CONTROL REGISTER 281
- DCLKnDIV + 1 299
- DCLKnCMP + 1 299
- 10 PWM TIMER 312
- PWM TIMER OPERATION 314
- 50 110 4040 6020 317
- 3 7 9 10 317
- Inverter off 319
- Inverter on 319
- PWM TIMER CONTROL REGISTERS 322
- BLOCK DIAGRAM 333
- UART SPECIAL REGISTERS 341
- Delta CTS 350
- Read_UMSTAT 350
- 12 USB HOST CONTROLLER 354
- 13 USB DEVICE CONTROLLER 356
- Non Indexed Registers 358
- 14 INTERRUPT CONTROLLER 378
- 15 LCD CONTROLLER 396
- STN LCD CONTROLLER OPERATION 399
- , B = 2 399
- LCD Panel 404
- Full Frame Timing(MMODE = 0) 410
- TFT LCD CONTROLLER OPERATION 411
- P1 P2 P3 P4 P5 412
- P6 P7 P8 P10 P11 P12P9 414
- LEGEND: 424
- AIN5, AIN6, AIN7) for ADC 444
- 17 REAL TIME CLOCK 450
- 15~ 22pF 452
- 18 WATCHDOG TIMER 460
- 19 MMC/SD/SDIO CONTROLLER 464
- SD OPERATION 465
- SDIO OPERATION 466
- SDI SPECIAL REGISTERS 467
- 20 IIC-BUS INTERFACE 478
- Clock to Output 482
- 21 IIS-BUS INTERFACE 492
- FUNCTIONAL DESCRIPTIONS 493
- AUDIO SERIAL INTERFACE FORMAT 494
- 22 SPI 500
- SPI OPERATION 502
- SPI TRANSFER FORMAT 503
- SPI SPECIAL REGISTERS 505
- 23 CAMERA INTERFACE 510
- Figure 23-1. CAMIF Overview 511
- CAMERA INTERFACE OPERATION 514
- ITU-601/656 YCbCr 517
- 4:2:2 8-bit input timing 517
- Little endian method 517
- < Frame Capture Start > 518
- ImgCptEn(cmd) 519
- LastIRQEn 519
- FrameCnt 519
- 1 = Window offset enable 521
- 24 AC97 CONTROLLER 538
- AC97 CONTROLLER OPERATION 539
- INTERNAL DATA PATH 540
- OPERATION FLOW CHART 541
- SDATA_OUT 542
- SDATA_IN 542
- 0 1 2 3 4 5 6 7 8 9 10 11 12 542
- AC97 POWERDOWN 544
- 25 BUS PRIORITIES 550
- 26 MECHANICAL DATA 552
- 27 ELECTRICAL DATA 554
- Application 555
- (Unit: mA) 560
- (internal) 561
- 1. HSYNC period 591
- 2. VCLK period 591
- SDAH) is minimum 0ns 592
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