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IIS-BUS INTERFACE S3C2440A RISC MICROPROCESSOR
21-2
BLOCK DIAGRAM
ADDR
DATA
CNTL
PCLK
BRFC
IPSR_A
IPSR_B
TxFIFO
RxFIFO
SCLKG
CHNC
SFTR
LRCK
SCLK
SD
CDCLK
MPLLin
Figure 21-1. IIS-Bus Block Diagram
FUNCTIONAL DESCRIPTIONS
Bus interface, register bank, and state machine (BRFC): Bus interface logic and FIFO access are controlled by the
state machine.
5-bit dual prescaler (IPSR): One prescaler is used as the master clock generator of the IIS bus interface and the
other is used as the external CODEC clock generator.
64-byte FIFOs (TxFIFO and RxFIFO): In transmit data transfer, data are written to TxFIFO, and, in the receive data
transfer, data are read from RxFIFO.
Master IISCLK generator (SCLKG): In master mode, serial bit clock is generated from the master clock.
Channel generator and state machine (CHNC): IISCLK and IISLRCK are generated and controlled by the channel
state machine.
16-bit shift register (SFTR): Parallel data is shifted to serial data output in the transmit mode, and serial data input
is shifted to parallel data in the receive mode.
TRANSMIT OR RECEIVE ONLY MODE
Normal Transfer
IIS control register has FIFO ready flag bits for transmit and receive FIFOs. When FIFO is ready to transmit data, the
FIFO ready flag is set to '1' if transmit FIFO is not empty. If transmit FIFO is empty, FIFO ready flag is set to '0'.
While receiving FIFO is not full, the FIFO ready flag for receive FIFO is set to '1' ; it indicates that FIFO is ready to
receive data. If receive FIFO is full, FIFO ready flag is set to '0'. These flags can determine the time that CPU is to
write or read FIFOs. Serial data can be transmitted or received while the CPU is accessing transmit and receive
FIFOs in this way.
- S3C2440A 1
- Important Notice 2
- Table of Contents 3
- Table of Contents (Continued) 10
- List of Figures 22
- List of Figures (Continued) 23
- List of Tables 28
- List of Tables (Continued) 29
- 1 PRODUCT OVERVIEW 30
- FEATURES 31
- FEATURES (Continued) 32
- PIN ASSIGNMENTS 35
- @nRESET4 OSCin 47
- ← W Control and status group 56
- ← W R/W DMA 0 initial source 57
- ← W R/W DMA 3 initial source 57
- ← W RW Input source format 60
- ← W R/W Timer configuration 62
- ← W R/W Watchdog timer mode 64
- ← W R/W IIC control 64
- ← W R/W Port A control 65
- ← W R/W Reserved 66
- 2 PROGRAMMER'S MODEL 69
- THUMB State 74
- ARM State 74
- Lo-RegistersHi-Registers 74
- 3 ARM INSTRUCTION SET 85
- THE CONDITION FIELD 88
- BRANCH AND EXCHANGE (BX) 89
- [24] Link bit 91
- Examples 92
- DATA PROCESSING 93
- [6:5] Shift type 96
- [11:7] Shift amount 96
- [11:8] Shift register 96
- PSR TRANSFER (MRS, MSR) 102
- [19:16] Destination Register 106
- [20] Set Condition Code 106
- [21] Accumulate 106
- [31:28] Condition Field 106
- Big-Endian Configuration 114
- 1 = Up: add offset to base 118
- [6][5] S H 118
- SINGLE DATA SWAP (SWP) 131
- SOFTWARE INTERRUPT (SWI) 133
- 31 2427 19 15 135
- Cond CRm 135
- 28 16 111223 20 135
- 0CpCp#CRdCRn1110 CP Opc 135
- 8 7 5 4 3 0 135
- [11:8] Coprocessor Number 137
- EXAMPLES 139
- 4 THUMB INSTRUCTION SET 149
- FORMAT SUMMARY 150
- [2:0] Destination Register 153
- [5:3] Source Register 153
- [10:6] Immediate Vale 153
- [12:11] Opcode 153
- [8:6] Register/Immediate Vale 155
- [9] Opcode 155
- [10] Immediate Flag 155
- [7:0] Immediate Vale 157
- FORMAT 4: ALU OPERATIONS 159
- [6] Hi Operand Flag 2 161
- [7] Hi Operand Flag 1 161
- [9:8] Opcode 161
- FORMAT 6: PC-RELATIVE LOAD 164
- [5:3] Base Register 166
- [8:6] Offset Register 166
- [10] Byte/Word Flag 166
- [11] Load/Store Flag 166
- [10] Sign-Extended Flag 168
- [11] H Flag 168
- [10:6] Offset Register 170
- [12] Byte/Word Flad 170
- INSTRUCTION CYCLE TIMES 171
- [10:6] Immediate Value 172
- [7:0] Immediate Value 174
- [10:8] Destination Register 174
- [11] Load/Store Bit 174
- [7:0] 8-bit Unsigned Constant 176
- [11] Source 176
- [6:0] 7-bit Immediate Value 178
- [7] Sign Flag 178
- FORMAT 14: PUSH/POP REGISTERS 179
- [7:0] Register List 181
- [10:8] Base Register 181
- [7:0] 8-bit Signed Immediate 182
- [11:8] Condition 182
- [7:0] Comment Field 184
- [10:0] Immediate Value 185
- [11] Low/High Offset Bit 186
- LR := temp 187
- INSTRUCTION SET EXAMPLES 188
- 5 MEMORY CONTROLLER 193
- Table 5-1. Bank 6/7 Addresses 195
- FUNCTION DESCRIPTION 196
- ROM Memory Interface Examples 200
- PROGRAMMABLE ACCESS CYCLE 204
- 6 NAND FLASH CONTORLLER 213
- NAND FLASH MEMORY TIMING 216
- SOFTWARE MODE 217
- ECC (ERROR CORRECTION CODE) 219
- NAND FLASH MEMORY MAPPING 221
- CLOCK & POWER MANAGEMENT 235
- FUNCTIONAL DESCRIPTION 236
- HDIVN PDIVN 237
- Management 244
- S3C2440A 251
- approximately 7 NOP) 255
- OVERVIEW 260
- DMA REQUEST SOURCES 261
- DMA OPERATION 261
- Read Write 262
- Demand Mode 263
- Handshake Mode 263
- Double Synch 264
- DMA SPECIAL REGISTERS 266
- 9 I/O PORTS 274
- PORT CONTROL DESCRIPTIONS 280
- I/O PORT CONTROL REGISTER 281
- DCLKnDIV + 1 299
- DCLKnCMP + 1 299
- 10 PWM TIMER 312
- PWM TIMER OPERATION 314
- 50 110 4040 6020 317
- 3 7 9 10 317
- Inverter off 319
- Inverter on 319
- PWM TIMER CONTROL REGISTERS 322
- BLOCK DIAGRAM 333
- UART SPECIAL REGISTERS 341
- Delta CTS 350
- Read_UMSTAT 350
- 12 USB HOST CONTROLLER 354
- 13 USB DEVICE CONTROLLER 356
- Non Indexed Registers 358
- 14 INTERRUPT CONTROLLER 378
- 15 LCD CONTROLLER 396
- STN LCD CONTROLLER OPERATION 399
- , B = 2 399
- LCD Panel 404
- Full Frame Timing(MMODE = 0) 410
- TFT LCD CONTROLLER OPERATION 411
- P1 P2 P3 P4 P5 412
- P6 P7 P8 P10 P11 P12P9 414
- LEGEND: 424
- AIN5, AIN6, AIN7) for ADC 444
- 17 REAL TIME CLOCK 450
- 15~ 22pF 452
- 18 WATCHDOG TIMER 460
- 19 MMC/SD/SDIO CONTROLLER 464
- SD OPERATION 465
- SDIO OPERATION 466
- SDI SPECIAL REGISTERS 467
- 20 IIC-BUS INTERFACE 478
- Clock to Output 482
- 21 IIS-BUS INTERFACE 492
- FUNCTIONAL DESCRIPTIONS 493
- AUDIO SERIAL INTERFACE FORMAT 494
- 22 SPI 500
- SPI OPERATION 502
- SPI TRANSFER FORMAT 503
- SPI SPECIAL REGISTERS 505
- 23 CAMERA INTERFACE 510
- Figure 23-1. CAMIF Overview 511
- CAMERA INTERFACE OPERATION 514
- ITU-601/656 YCbCr 517
- 4:2:2 8-bit input timing 517
- Little endian method 517
- < Frame Capture Start > 518
- ImgCptEn(cmd) 519
- LastIRQEn 519
- FrameCnt 519
- 1 = Window offset enable 521
- 24 AC97 CONTROLLER 538
- AC97 CONTROLLER OPERATION 539
- INTERNAL DATA PATH 540
- OPERATION FLOW CHART 541
- SDATA_OUT 542
- SDATA_IN 542
- 0 1 2 3 4 5 6 7 8 9 10 11 12 542
- AC97 POWERDOWN 544
- 25 BUS PRIORITIES 550
- 26 MECHANICAL DATA 552
- 27 ELECTRICAL DATA 554
- Application 555
- (Unit: mA) 560
- (internal) 561
- 1. HSYNC period 591
- 2. VCLK period 591
- SDAH) is minimum 0ns 592
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