NAND FLASH CONTROLLER S3C2440A RISC MICROPROCESSOR
6-14
CONTROL REGISTER (Continued)
NFCONT Bit Description Initial State
SpareECCLock [6] Lock spare area ECC generation.
0: Unlock spare ECC 1: Lock spare ECC
Spare area ECC status register is FSECC(0x4E000034)
1
MainECCLock [5] Lock Main data area ECC generation
0: Unlock main data area ECC generation
1: Lock main data area ECC generation
Main area ECC status register is NFMECC0/1
(0x4E00002C/30)
1
InitECC [4] Initialize ECC decoder/encoder(Write-only)
1: Initialize ECC decoder/encoder
0
Reserved [2:3] Reserved 00
Reg_nCE [1] NAND Flash Memory nFCE signal control
0: Force nFCE to low (Enable chip select)
1: Force nFCE to high (Disable chip select)
Note: During boot time, it is controlled automatically.
This value is only valid while MODE bit is 1
1
MODE [0] NAND flash controller operating mode
0: NAND flash controller disable (Don’t work)
1: NAND flash controller enable
0
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